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n u m icro ? j an 31 , 201 9 page 1 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet numicro? nuc200 /220 series datas heet the information described in this document is the exclusive intellectual property of nuvoton technology corporation and shall not be reproduced without permission from nuvoton. nuvoton is providing this document only for reference purposes of numicro tm microcontroller based system design. nuvoton assumes no responsibility for errors or omissions. all data and specification s are subject to change without notice. for additional information or questions, please contact: nuvoton technology corporation. www.nuvoton.com
n u m icro ? j an 31 , 201 9 page 2 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet t able of co ntents list of figures ................................ ................................ ................................ ................................ .. 5 list of tables ................................ ................................ ................................ ................................ .... 6 1 general description ................................ ................................ ................................ ......... 7 2 featur es ................................ ................................ ................................ ................................ . 8 2.1 numicro ? nuc200 features C advanced line ................................ .............................. 8 2.2 numicro ? nuc220 features C usb line ................................ ................................ .... 12 3 parts information li st and pin configura tion ................................ .................... 16 3.1 numicro ? nuc200/220xxxan selection guide ................................ ........................... 16 3.1.1 numicro ? nuc200 advanced line selection guide ................................ ...................... 16 3.1.2 numicro ? nuc220 usb line selection guide ................................ .............................. 16 3.2 pin configuration ................................ ................................ ................................ .......... 18 3.2.1 numicro ? nuc200 pin diagram ................................ ................................ .................... 18 3.2.2 numicro ? nuc220 pin diagram ................................ ................................ .................... 21 3.3 pin description ................................ ................................ ................................ .............. 24 3.3.1 numicro ? nuc200 pin description ................................ ................................ ................ 24 3.3.2 numicro ? nuc220 pin description ................................ ................................ ................ 31 4 block diagram ................................ ................................ ................................ .................... 38 4.1 numicro ? nuc200 block diagram ................................ ................................ .............. 38 4.2 numicro ? nuc220 block diagram ................................ ................................ .............. 39 5 functional descripti on ................................ ................................ ................................ .. 40 5.1 arm ? cortex? - m0 core ................................ ................................ .............................. 40 5.2 system manager ................................ ................................ ................................ ........... 42 5.2.1 overview ................................ ................................ ................................ ........................ 42 5.2.2 system reset ................................ ................................ ................................ ................. 42 5.2.3 system power distribution ................................ ................................ ............................. 43 5.2.4 system memory map ................................ ................................ ................................ ...... 45 5.2.5 system timer (systick) ................................ ................................ ................................ . 47 5.2.6 nested vectored interrupt controller (nvic) ................................ ................................ .. 48 5.2.7 system control (scs) ................................ ................................ ................................ .... 54 5.3 clock controller ................................ ................................ ................................ ............ 54 5.3.1 overview ................................ ................................ ................................ ........................ 54 5.3.2 clock ge nerator ................................ ................................ ................................ ............. 57 5.3.3 system clock and systick clock ................................ ................................ ................... 58 5.3.4 peripherals clock ................................ ................................ ................................ ........... 59 5.3.5 power - down mode clock ................................ ................................ ................................ 59 5.3.6 frequency divider output ................................ ................................ ............................... 60 5.4 usb device controller (usb) ................................ ................................ ....................... 61 5.4.1 overview ................................ ................................ ................................ ........................ 61 5.4.2 features ................................ ................................ ................................ ......................... 61 5.5 general purpose i/o (gpio) ................................ ................................ ........................ 62 5.5.1 overview ................................ ................................ ................................ ........................ 62 5.5.2 features ................................ ................................ ................................ ......................... 62
n u m icro ? j an 31 , 201 9 page 3 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.6 i 2 c serial interface controller (i 2 c) ................................ ................................ ............... 63 5.6.1 overview ................................ ................................ ................................ ........................ 63 5.6.2 features ................................ ................................ ................................ ......................... 64 5.7 pwm generator and capture timer (pwm) ................................ ................................ 65 5.7.1 overview ................................ ................................ ................................ ........................ 65 5.7.2 features ................................ ................................ ................................ ......................... 66 5.8 real time clock (rtc) ................................ ................................ ................................ . 67 5.8.1 overview ................................ ................................ ................................ ........................ 67 5.8.2 features ................................ ................................ ................................ ......................... 67 5.9 serial per ipheral interface (spi) ................................ ................................ ................... 68 5.9.1 overview ................................ ................................ ................................ ........................ 68 5.9.2 features ................................ ................................ ................................ ......................... 68 5.10 timer controller (tmr) ................................ ................................ ................................ . 69 5.10.1 overview ................................ ................................ ................................ ...................... 69 5.10.2 features ................................ ................................ ................................ ....................... 69 5.11 watchdog timer (wdt) ................................ ................................ ................................ 70 5.11.1 overview ................................ ................................ ................................ ...................... 70 5.11.2 featu res ................................ ................................ ................................ ....................... 70 5.12 window watchdog timer (wwdt) ................................ ................................ ............... 70 5.12.1 overview ................................ ................................ ................................ ...................... 70 5.12.2 features ................................ ................................ ................................ ....................... 70 5.13 uart interface controller (uart) ................................ ................................ ............... 71 5.13.1 overview ................................ ................................ ................................ ...................... 71 5.13.2 features ................................ ................................ ................................ ....................... 73 5.14 ps/2 device controller (ps2d) ................................ ................................ ..................... 74 5.14.1 overview ................................ ................................ ................................ ...................... 74 5.14.2 features ................................ ................................ ................................ ....................... 74 5.15 i 2 s controller (i 2 s) ................................ ................................ ................................ ......... 75 5. 15.1 overview ................................ ................................ ................................ ...................... 75 5.15.2 features ................................ ................................ ................................ ....................... 75 5.16 analog - to - digital converter (adc) ................................ ................................ ............... 76 5.16.1 overview ................................ ................................ ................................ ...................... 76 5.16.2 features ................................ ................................ ................................ ....................... 76 5.17 analog comparator (acmp) ................................ ................................ ......................... 77 5.17.1 overview ................................ ................................ ................................ ...................... 77 5.17.2 features ................................ ................................ ................................ ....................... 77 5.18 pdma controller (pdma) ................................ ................................ ............................. 78 5.18.1 overview ................................ ................................ ................................ ...................... 78 5.18.2 features ................................ ................................ ................................ ....................... 78 5.19 smart card host interface (sc) ................................ ................................ .................... 79 5.19.1 overview ................................ ................................ ................................ ...................... 79 5.19.2 featu res ................................ ................................ ................................ ....................... 79 5.20 flash memory controller (fmc) ................................ ................................ .... 80 5.20.1 overview ................................ ................................ ................................ ...................... 80
n u m icro ? j an 31 , 201 9 page 4 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.20.2 featu res ................................ ................................ ................................ ....................... 80 6 application circuit ................................ ................................ ................................ ........... 81 7 electrical character istics ................................ ................................ ......................... 82 7.1 absolute maximum ratings ................................ ................................ .......................... 82 7.2 dc electrical characteristics ................................ ................................ ........................ 83 7.3 ac electrical characteristics ................................ ................................ ........................ 88 7.3.1 external 4~24 mhz high speed oscillator ................................ ................................ ..... 88 7.3.2 external 4~24 mhz high speed crystal ................................ ................................ ......... 88 7.3.3 external 32.768 khz low speed crystal oscillator ................................ ........................ 89 7.3.4 internal 22.1184 mhz high speed oscillator ................................ ................................ .. 89 7.3.5 internal 10 khz low speed oscillator ................................ ................................ ............. 90 7.4 analog characteristics ................................ ................................ ................................ .. 90 7. 4.1 12 - bit saradc specification ................................ ................................ ......................... 90 7.4.2 ldo and power management specification ................................ ................................ ... 90 7.4.3 low voltage reset specification ................................ ................................ .................... 92 7.4.4 brown - out detector specification ................................ ................................ ................... 92 7.4.5 power - on reset specification ................................ ................................ ........................ 92 7.4.6 temperature sensor specification ................................ ................................ ................. 93 7.4.7 comparator specification ................................ ................................ ............................... 93 7.4.8 usb phy specification ................................ ................................ ................................ .. 94 7.5 flash dc electrical characteristics ................................ ................................ .............. 96 8 package dimensions ................................ ................................ ................................ ......... 97 8.1 10 0 - pin lqfp (14x14x1.4 mm footprint 2.0 mm) ................................ ......................... 97 8.2 64 - pin lqfp (7x7x1.4 mm footprint 2.0 mm) ................................ ............................... 98 8.3 48 - pin lqfp (7x7x1.4 mm footprint 2.0 mm) ................................ ............................... 99 9 revision history ................................ ................................ ................................ .............. 100
n u m icro ? j an 31 , 201 9 page 5 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet list of figures figure 3 - 1 numicro ? nuc 2 00 series s election c ode ................................ ................................ .. 17 figure 3 - 2 numicro ? nuc 2 00 vxxan lqfp 100 - pin diagram ................................ ..................... 18 figure 3 - 3 numicro ? nuc 2 00 sxxan lqfp 64 - pin diagram ................................ ....................... 19 figure 3 - 4 numicro ? nuc 2 00 lxxan lqfp 48 - pin diagram ................................ ........................ 20 figure 3 - 5 numicro ? nuc 2 20 vxxan lqfp 100 - pin diagram ................................ ..................... 21 figure 3 - 6 numicro ? nuc 2 20 sxxan lqfp 64 - pin diagram ................................ ....................... 22 figure 3 - 7 numicro ? nuc 2 20 lxxan lqfp 48 - pin diagram ................................ ........................ 23 figure 4 - 1 numicro ? nuc200 block diagram ................................ ................................ .............. 38 figure 4 - 2 numicro ? nuc220 block diagram ................................ ................................ .............. 39 figure 5 - 1 functional controller diagram ................................ ................................ ...................... 40 figure 5 - 2 numicro ? nuc200 power distribution diagram ................................ .......................... 43 figure 5 - 3 numicro ? nuc220 power distribution diagram ................................ .......................... 44 figure 5 - 4 clock generator global view diagram ................................ ................................ ......... 55 figure 5 - 5 clock generator block diagram ................................ ................................ ................... 57 figure 5 - 6 system clock block diagram ................................ ................................ ....................... 58 figure 5 - 7 systick clock control block diagram ................................ ................................ .......... 58 figure 5 - 8 clock source of frequency divider ................................ ................................ .............. 60 figure 5 - 9 frequency divider block diagram ................................ ................................ ................ 60 figure 5 - 18 i 2 c bus timing ................................ ................................ ................................ ............ 63 figure 6 - 1 typical crystal application circuit ................................ ................................ ................ 89
n u m icro ? j an 31 , 201 9 page 6 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet list of tables table 1 - 1 connectivity support table ................................ ................................ .............................. 7 table 5 - 1 address space assignments for on - chip controllers ................................ ................... 46 table 5 - 2 exception model ................................ ................................ ................................ ............ 49 table 5 - 3 system interrupt map ................................ ................................ ................................ ..... 50 table 5 - 4 vector table format ................................ ................................ ................................ ...... 51 table 5 - 9 uart baud rate equation ................................ ................................ ............................ 71 table 5 - 10 uart baud rate setting table ................................ ................................ ................... 72
n u m icro ? j an 31 , 201 9 page 7 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 1 general description the numicro ? nuc 2 00 series 32 - bit microcontrollers is embedded with the newest arm ? cortex? - m0 core with a cost equivalent to traditional 8 - bit mcu for industrial control and applications requiring rich communication interfaces. t he numicro ? nuc 2 00 series include s nuc 2 00 and nuc 2 20 product line s . the numicro ? nuc 2 00 advanced line is embed ded with the cortex? - m0 core running up to 50 mhz and features 32k/64k/128k byte s flash, 8k/16k byte s embedded sram, and 4 kbyte s loader rom for the isp. it is also equip ped with plenty of peripheral devices, such as timers, watchdog timer, window wat chdog timer, rtc, pdma with crc calculation uni t , uart, spi, i 2 c, i 2 s, pwm timer, gpio, ps / 2, smart card host, 12 - bit adc, analog comparator, low voltage reset controller and brown - out detector. the numicro ? nuc 2 20 usb line with usb 2.0 full - speed function is embed ded with the cortex? - m0 core running up to 50 mhz and features 32k/64k/128k byte s flash, 8k/16k byte s embedded sram, and 4 kbyte s loader rom for the isp. it is also equip ped with plenty of peripheral dev ices, such as timers, watchdog timer, window watchdog timer, rtc, pdma with crc calculation uni t , uart, spi, i 2 c, i 2 s, pwm timer, gpio, ps / 2, usb 2.0 fs device, smart card host, 12 - bit adc, analog comparator, low voltage reset controller and brown - out dete ctor. product line uart spi i 2 c usb lin can ps / 2 i 2 s sc nuc 2 00 nuc 2 20 table 1 - 1 connectivity support table
n u m icro ? j an 31 , 201 9 page 8 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 2 features the equipped features are dependent on the product line and their sub product s. 2.1 numicro ? C advanced line ? arm ? cortex? - m0 core C r uns up to 50 mhz C one 24 - bit system timer C supports low power sleep mode C single - cycle 32 - bit hardware multiplier C nvic for the 32 interrupt inputs, each with 4 - levels of priority C serial wire debug supports with 2 watchpoints/4 breakpoints ? buil t - in ldo for wide operating voltage range d from 2.5 v to 5.5 v ? flash memory C 32k/64k/128k bytes flash for program code C 4 kb flash for isp loader C support s in - s ystem - p rogram (isp) and in - application - program (iap) application code update C 512 byte page erase for flash C configurable data flash address and size for 128 kb system, fixed 4 kb data flash for the 32 kb and 64 kb system C support s 2 - wired icp update through swd/ice interface C support s fast parallel programming mode by external programmer ? sram memory C 8k/16k bytes embedded sram C support s pdma mode ? pdma (peripheral dma) C support s 9 channels pdma for automatic data transfer between sram and peripherals C support s crc calculation with four common polynomials, crc - ccitt, crc - 8, crc - 16 and crc - 32 ? clock control C flexible selection for different applications C built - in 22.1184 mhz high speed oscillator for system operation ? trimmed to 1 % at +25 and v dd = 5 v ? trimmed t o 3 % at - 40 ~ +85 and v dd = 2.5 v ~ 5.5 v C built - in 10 k hz low speed oscillator for watchdog timer and wake - up operation C support s one pll, up to 50 mhz, for high performance system operation C external 4~24 mhz high speed crystal input for precise timing operation C external 32.768 khz low speed crystal input for rtc function and low power system operation ? gpio C four i/o modes: ? quasi - bidirection al ? push - p ull output ? open - d rain output ? input only with high impendence C ttl/schmitt trigger input selectable C i/o pin configured as interrupt source with edge/level setting ? timer
n u m icro ? j an 31 , 201 9 page 9 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet C support s 4 sets of 32 - bit timers with 24 - bit up - timer and one 8 - bit prescale counter C independent clock source for each timer C provides one - shot, periodic, toggle and continuous counting op eration modes C support s event counting function C support s input capture function ? watchdog timer C multiple clock sources C 8 selectable time - out period from 1. 6 ms ~ 26 .0 sec (depend ing on clock source) C wake - up from p ower - down or i dle mode C interrupt or reset selectable on watchdog time - out ? window watchdog timer C 6 - bit down counter with 11 - bit prescale for wide range window selected ? rtc C support s software compensation by setting frequency compensate register (fcr) C support s rtc counter (second, minute, hour) and calendar counter (day, month, year) C support s alarm registers (second, minute, hour, day, month, year) C selectable 12 - hour or 24 - hour mode C automatic leap year recognition C support s periodic time tick interrupt with 8 pe riod options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second C supports battery power pin ( v bat ) C support s wake - up function ? pwm /capture C u p to four built - in 16 - bit pwm generators provid ing eight pwm outputs or four complementary paired pwm outputs C each pwm generator equipped with one clock source selector, one clock divider, one 8 - bit prescaler and one dead - zone generator for complementary paired pwm C up to eight 16 - bit digital c apture timers (shared with pwm timers) provid ing eight rising/falling capture inputs C support s capture interrupt ? uart C up to three uart controllers C uart ports with flow control (txd, rxd, n cts and n rts) C uart0 with 6 4 - byte fifo is for high speed C uart1/2(optional) with 1 6 - byte fifo for standard device C support s irda (sir) and lin function C support s rs - 485 9 - bit mode and direction control C programmable baud - rate generator up to 1/16 system clock C support s pdma mode ? spi C up to four sets of spi controller s C the maximum spi clock rate of master can up to 36 mhz ( chip working at 5v) C the maximum spi clock rate of slave can up to 18 mhz (chip working at 5v) C support s spi m aster/ s lave mode C full duplex synchronous serial data transfer C variable length of transfer data from 8 to 32 bit s C msb or lsb first data transfer C rx and tx on both rising or falling edge of serial clock independently C two slave/device select lines in m aster mode , and one slave/device select line in s lave mode C support s b yte s uspend mode in 32 - bit transmission
n u m icro ? j an 31 , 201 9 page 10 of 1 00 revision 1.01 nuc 2 00/ 2 2 0 datasheet C support s pdma mode C support s three wire, no slave select signal, bi - direction interfac e ? i 2 c C up to two sets of i 2 c device C master/slave mode C bidirectional data transfer between masters and slaves C multi - master bus (no central master) C arbitration between simultaneously transmitting masters without corruption of serial data on the bus C ser ial clock synchronization allow ing devices with different bit rates to communicate via one serial bus C serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer C p rogrammable clocks allow ing for versatile rate control C support s multiple address recognition (four slave address with mask option) C support s wake - up function ? i 2 s C interface with external audio codec C operate as either m aster or s lave mode C capable of handling 8 - , 16 - , 24 - and 32 - bit word sizes C supports m ono and stereo audio data C supports i 2 s and msb justified data format C provides t wo 8 word fifo data buffers, one for transmit ting and the other for receiv ing C generates interrupt requests when buffer levels cross a programmable boundary C support s two dma requests, one for transmit ting and the other for receiv ing ? ps/2 device C host communication inhibit and request to send detection C reception frame error detection C programmable 1 to 16 bytes transmit buffer to reduce cp u intervention C double buffer for data reception C s oftware override bus ? adc C 12 - bit sar adc with 7 6 0 k sps C up to 8 - ch single - end input or 4 - ch differential input C single scan/single cycle scan/continuous scan C each channel with individual result register C scan on enabled channels C threshold voltage detection C conversion start ed by software programming or external input C support s pdma mode ? analog comparator C up to two analog comparator s C external input or internal b and - gap voltage selectable at negative node C interrupt when compare result change C supports p ower - down wake - up ? smart card host (sc) C compliant to iso - 7816 - 3 t=0, t=1 C support s up to t hree iso - 7816 - 3 ports C separate receive / transmit 4 bytes entry fifo for data payloads C programmable transmission clock frequency
n u m icro ? j an 31 , 201 9 page 11 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet C programmable receiver buffer trigger level C programmable guard time selection (11 etu ~ 266 etu) C one 24 - bit and two 8 - bit time - out counters for answer to request (atr) and waiting times processing C support s auto inverse convention function C support s transmitter and receiver error retry and error limit function C support s hardware activation sequence process C support s hardware warm reset sequence process C support s hardware deactivation sequence process C support s hardware auto deactivation sequence when det ect ing the card removal ? 96 - bit unique id (uid) ? o ne built - in t emperature sensor with 1 resolution ? brown - out d etector C with 4 levels: 4. 4 v/3. 7 v/2.7 v/2.2 v C support s brown - out interrupt and reset option ? low voltage reset C threshold voltage level : 2.0 v ? operating temperature: - 40 ~ 85 ? packages: C all green package (rohs) C lqfp 100 - pin / 64 - pin / 48 - pin
n u m icro ? j an 31 , 201 9 page 12 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 2.2 numicro ? C usb line ? arm ? cortex? - m0 core C r uns up to 50 mhz C one 24 - bit system timer C supports low power sleep mode C single - cycle 32 - bit hardware multiplier C nvic for the 32 interrupt inputs, each with 4 - levels of priority C serial wire debug supports with 2 watchpoints/4 breakpoints ? buil t - in ldo for wide operating voltage ranges from 2.5 v to 5.5 v ? flash memory C 32k/64k/128k bytes flash for pr ogram code C 4 kb flash for isp loader C support s in - s ystem - p rogram (isp) and in - application - program (iap) application code update C 512 byte page erase for flash C configurable data flash address and size for 128 kb system, fixed 4 kb data flash for the 32 kb and 64 kb system C support s 2 - wired icp update through swd/ice interface C support s fast parallel programming mode by external programmer ? sram memory C 8k/16k bytes embedded sram C support s pdma mode ? pdma (peripheral dma) C support s 9 channels pdma for automatic data t ransfer between sram and peripherals C support s crc calculation with four common polynomials, crc - ccitt, crc - 8, crc - 16 and crc - 32 ? clock control C flexible selection for different applications C built - in 22.1184 mhz high speed oscillator for system operation ? trimmed to 1 % at +25 and v dd = 5 v ? trimmed to 3 % at - 40 ~ +85 and v dd = 2.5 v ~ 5.5 v C built - in 10 k hz low speed oscillator for watchdog timer and wake - up operation C support s one pll, up to 50 mhz, for high performance system operation C external 4~24 mhz high speed crystal input for usb and precise timing operation C external 32.768 khz low speed crystal input for rtc function and low power system operation ? gpio C four i/o modes: ? quasi - bidirection al ? push - p ull output ? open - d rain output ? input on ly with high impendence C ttl/schmitt trigger input selectable C i/o pin configured as interrupt source with edge/level setting ? timer C support s 4 sets of 32 - bit timers with 24 - bit up - timer and one 8 - bit prescale counter C independent clock source for each timer C provides one - shot, periodic, toggle and continuous counting operation modes
n u m icro ? j an 31 , 201 9 page 13 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet C support s event counting function C support s input capture function ? watchdog timer C multiple clock sources C 8 selectable time - out period from 1. 6 ms ~ 26 .0 sec (depend ing on clock source) C w ake - up from p ower - down or i dle mode C interrupt or reset selectable on watchdog time - out ? window watchdog timer C 6 - bit down counter with 11 - bit prescale for wide range window selected ? rtc C support s software compensation by setting frequency compensate register (fcr) C support s rtc counter (second, minute, hour) and calendar counter (day, month, year) C support s alarm registers (second, minute, hour, day, month, year) C selectable 12 - hour or 24 - hour mode C a utomatic leap year recognition C support s periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second C supports battery power pin (v bat ) C support s wake - up function ? pwm /capture C u p to four built - in 16 - bit pwm generators provid ing eight pwm outputs or four complementary paired pwm outputs C each pwm generator equipped with one clock source selector, one clock divider, one 8 - bit prescaler and one dead - zone generator for complementary paired pwm C up to eight 16 - bit digital c ap ture timers (shared with pwm timers) provid ing eight rising/falling capture inputs C support s c apture interrupt ? uart C up to three uart controllers C uart ports with flow control (txd, rxd, n cts and n rts) C uart0 with 6 4 - byte fifo is for high speed C uart1/2(optional) with 1 6 - byte fifo for standard device C support s irda (sir) and lin function C support s rs - 485 9 - bit mode and direction control C programmable baud - rate generator up to 1/16 system clock C support s pdma mode ? spi C up to four sets of spi controller s C the maximum spi clock rate of master can up to 36 mhz (chip working at 5v) C the maximum spi clock rate of slave can up to 18 mhz (chip working at 5v) C support s spi m aster/ slave mode C full duplex synchronous serial data transfer C variable length of transfer data from 8 to 32 bit s C msb or lsb first data transfer C rx and tx on both rising or falling edge of serial clock independently C two slave/device select lines in master mode , and one slave/device select line in slave mode C support s b yte s uspend mode in 32 - bit transmission C support s pdma mode C support s three wire, no slave select signal, bi - direction interfac e
n u m icro ? j an 31 , 201 9 page 14 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet ? i 2 c C up to two sets of i 2 c device C master/ slave mode C bidirectional data transfer between masters and slaves C multi - master bus (no central master) C arbitration between simultaneously transmitting masters without corruption of serial data on the bus C ser ial clock synchronization allow ing devices with different bit rates to communicate via one serial bus C serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer C programmable clocks allow ing for versatile rate control C support s multiple address recognition (four slave address with mask option) C support s wake - up function ? i 2 s C interface with external audio codec C operate as either m aster or s lave mode C capable of handling 8 - , 16 - , 24 - and 32 - bit word sizes C supports m ono and s tereo audio data C supports i 2 s and msb justified data format C provides t wo 8 word fifo data buffers, one for transmit ting and the other for receiv ing C generates interrupt requests when buffer levels cross a programmable boundary C support s two dma requests, one for transmit ting and the other for receiv ing ? ps/2 device C host communication inhibit and request to send detection C reception frame error detection C programmable 1 to 16 bytes transmit buffer to reduce cpu intervention C double buffer for data reception C software override bus ? usb 2.0 full - speed device C one set of usb 2.0 fs device 12 mbps C on - chip usb transceiver C provide s 1 interrupt source with 4 interrupt events C support s control, bulk in/out, interrupt and isochronous transfers C auto suspend function when no bus signaling for 3 ms C provide s 6 programmable endpoints C include s 512 bytes internal sram as usb buffer C provide s re mote wake - up capability ? adc C 12 - bit sar adc with 7 6 0 k sps C up to 8 - ch single - end input or 4 - ch differential input C single scan/single cycle scan/continuous scan C each channel with individual result register C scan on enabled channels C threshold voltage detection C conversion start ed by software programming or external input C support s pdma m ode ? analog comparator C up to two analog comparator s C external input or internal b and - gap voltage selectable at negative node
n u m icro ? j an 31 , 201 9 page 15 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet C interrupt when compare result change C support s p ower - down wake - up ? smart card host (sc) C compliant to iso - 7816 - 3 t=0, t=1 C support s up to t hree iso - 7816 - 3 ports C separate receive / transmit 4 bytes entry fifo for data payloads C programmable transmission clock frequency C programmable receiver buffer trigger level C progra mmable guard time selection (11 etu ~ 266 etu) C one 24 - bit and two 8 - bit time - out counters for answer to request (atr) and waiting times processing C support s auto inverse convention function C support s transmitter and receiver error retry and error limit function C support s hardware activation sequence process C support s hardware warm reset sequence process C support s hardware deactivation sequence process C support s hardware auto deactivation sequence when det ect ing the card removal ? 96 - bit unique id (uid) ? one built - in t emperature sensor with 1 resolution ? brown - out d etector C with 4 levels: 4. 4 v/3. 7 v/2.7 v/2.2 v C support s brown - out interrupt and reset option ? low voltage reset C threshold voltage level: 2.0 v ? operating temperature: - 40 ~ 85 ? packages: C all green package (rohs) C lqfp 100 - pin / 64 - pin / 48 - pin
n u m icro ? j an 31 , 201 9 page 16 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 3 parts information li st and pin configuratio n 3.1 numicro ? 3.1.1 numicro ? part number aprom ram data flash isp loader rom i/o timer connectivity i 2 s sc comp. pwm adc rtc isp ic p iap package uart spi i 2 c usb lin can nuc 2 00l c2 an 32 kb 8 kb 4 kb 4 kb up to 35 4x32 - bit 2 1 2 - - - 1 2 1 6 7 x12 - bit v v lqfp48 nuc 2 00l d2 an 64 kb 8 kb 4kb 4 kb up to 35 4x32 - bit 2 1 2 - - - 1 2 1 6 7 x12 - bit v v lqfp48 nuc 2 00l e3 an 128 kb 16 kb definable 4 kb up to 35 4x32 - bit 2 1 2 - - - 1 2 1 6 7 x12 - bit v v lqfp48 nuc 2 00 sc2 an 32 kb 8 kb 4 kb 4 kb up to 49 4x32 - bit 3 2 2 - - - 1 2 2 6 7 x12 - bit v v lqfp64 nuc 2 00 sd2 an 64 kb 8 kb 4kb 4 kb up to 49 4x32 - bit 3 2 2 - - - 1 2 2 6 7 x12 - bit v v lqfp64 nuc 2 00 se3 an 1 28 kb 16 kb definable 4 kb up to 49 4x32 - bit 3 2 2 - - - 1 2 2 6 7 x12 - bit v v lqfp64 nuc 2 00ve3 an 128 kb 16 kb definable 4 kb up to 8 3 4x32 - bit 3 4 2 - - - 1 3 2 8 8x12 - bit v v lqfp100 3.1.2 numicro ? part number aprom ram data flash isp loader rom i/o timer connectivity i 2 s sc comp. pwm adc rtc isp icp iap package uart spi i 2 c usb lin can nuc 2 20l c2 an 32 kb 8 kb 4 kb 4 kb up to 31 4x32 - bit 2 1 2 1 - - 1 2 1 4 7 x12 - bit v v lqfp48 nuc 2 20ld 2 an 64 kb 8 kb 4 kb 4 kb up to 31 4x32 - bit 2 1 2 1 - - 1 2 1 4 7 x12 - bit v v lqfp48 nuc 2 20le3 an 128 kb 16 kb definable 4 kb up to 31 4x32 - bit 2 1 2 1 - - 1 2 1 4 7 x12 - bit v v lqfp48 nuc 2 20 sc2 an 32 kb 8 kb 4 kb 4 kb up to 45 4x32 - bit 2 2 2 1 - - 1 2 2 6 7 x12 - bit v v lqfp64 nuc 2 20 sd2 an 64 kb 8 kb 8 kb 4 kb up to 45 4x32 - bit 2 2 2 1 - - 1 2 2 6 7 x12 - bit v v lqfp64 nuc 2 20 se3 an 128 kb 16 kb definable 4 kb up to 45 4x32 - bit 2 2 2 1 - - 1 2 2 6 7 x12 - bit v v lqfp64 nuc 2 20ve3 an 128 kb 16 kb definable 4 kb up to 7 9 4x32 - bit 3 4 2 1 - - 1 3 2 8 8x12 - bit v v lqfp100
n u m icro ? j an 31 , 201 9 page 17 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet figure 3 - 1 numicro ? nuc 2 00 series s election c ode n u c 2 0 - x x a r m - b a s e d 3 2 - b i t m i c r o c o n t r o l l e r 0 : a d v a n c e d l i n e 2 : u s b l i n e 3 : a u t o m o t i v e l i n e 4 : c o n n e c t i v i t y l i n e c p u c o r e 1 / 2 : c o r t e x - m 0 5 / 7 : a r m 7 9 : a r m 9 t e m p e r a t u r e n : - 4 0 r e s e r v e d x x f u n c t i o n 0 p a c k a g e t y p e l : l q f p 4 8 s : l q f p 6 4 v : l q f p 1 0 0 x r a m s i z e 1 : 4 k b 2 : 8 k b 3 : 1 6 k b a p r o m s i z e c : 3 2 k b d : 6 4 k b e : 1 2 8 k b
n u m icro ? j an 31 , 201 9 page 18 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 3.2 pin configuration 3.2.1 numicro ? 3.2.1.1 numicro ? nuc 2 0 0 vxx an lqfp 100 - pin figure 3 - 2 numicro ? nuc 2 00 vxx an lqfp 100 - pin diagram s c 1 _ r s t / a d c 5 / p a . 5 s c 1 _ c l k / a d c 6 / p a . 6 s c 1 _ d a t / a d c 7 / s p i 2 _ s s 1 / p a . 7 s p i 3 _ s s 1 / i n t 0 / p b . 1 4 c m p 1 _ o / p b . 1 3 v b a t x 3 2 _ i n x 3 2 _ o u t i 2 c 1 _ s c l / p a . 1 1 i 2 c 1 _ s d a / p a . 1 0 i 2 c 0 _ s c l / p a . 9 i 2 c 0 _ s d a / p a . 8 u a r t 1 _ r x d / p b . 4 u a r t 1 _ t x d / p b . 5 u a r t 1 _ n r t s / p b . 6 u a r t 1 _ n c t s / p b . 7 l d o _ c a p v d d v s s s c 1 _ c d / c m p 0 _ n / p c . 7 s c 0 _ c d / c m p 0 _ p / p c . 6 c m p 1 _ n / p c . 1 5 c m p 1 _ p / p c . 1 4 t m 0 _ e x t / i n t 1 / p b . 1 5 x t 1 _ o u t / p f . 0 x t 1 _ i n / p f . 1 n r e s e t c l k o / t m 0 / s t a d c / p b . 8 p a . 4 / a d c 4 / s c 1 _ p w r p a . 3 / a d c 3 / s c 0 _ d a t p a . 2 / a d c 2 / s c 0 _ c l k p a . 1 / a d c 1 / s c 0 _ r s t p a . 0 / a d c 0 / s c 0 _ p w r a v s s i c e _ c l k i c e _ d a t p a . 1 2 / p w m 0 / s c 2 _ d a t p a . 1 3 / p w m 1 / s c 2 _ c l k p a . 1 4 / p w m 2 / s c 2 _ r s t p a . 1 5 / p w m 3 / i 2 s _ m c l k / s c 2 _ p w r p c . 8 / s p i 1 _ s s 0 p c . 9 / s p i 1 _ c l k a v d d v s s v d d p v s s p c . 0 / s p i 0 _ s s 0 / i 2 s _ l r c k p c . 1 / s p i 0 _ c l k / i 2 s _ b c l k p c . 2 / s p i 0 _ m i s o 0 / i 2 s _ d i p c . 3 / s p i 0 _ m o s i 0 / i 2 s _ d o p d . 1 5 / u a r t 2 _ t x d p d . 1 4 / u a r t 2 _ r x d p d . 7 p d . 6 p b . 3 / u a r t 0 _ n c t s / t m 3 _ e x t / s c 2 _ c d p b . 2 / u a r t 0 _ n r t s / t m 2 _ e x t / c m p 0 _ o p b . 1 / u a r t 0 _ t x d p b . 0 / u a r t 0 _ r x d p e . 7 p e . 8 p e . 9 p e . 1 0 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 p c . 1 0 / s p i 1 _ m i s o 0 p c . 1 1 / s p i 1 _ m o s i 0 n u c 2 0 0 v x x a n l q f p 1 0 0 - p i n 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 p e . 1 5 p e . 1 4 p e . 1 3 s p i 3 _ s s 0 / p d . 8 s p i 3 _ c l k / p d . 9 s p i 3 _ m i s o 0 / p d . 1 0 s p i 3 _ m o s i 0 / p d . 1 1 s p i 3 _ m i s o 1 / p d . 1 2 s p i 3 _ m o s i 1 / p d . 1 3 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 p e . 1 1 p e . 1 2 p c . 4 / s p i 0 _ m i s o 1 p c . 5 / s p i 0 _ m o s i 1 p b . 9 / t m 1 / s p i 1 _ s s 1 p b . 1 0 / t m 2 / s p i 0 _ s s 1 p b . 1 1 / t m 3 / p w m 4 p e . 5 / t m 1 _ e x t / p w m 5 p e . 6 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 v s s v d d p c . 1 2 / s p i 1 _ m i s o 1 p c . 1 3 / s p i 1 _ m o s i 1 p e . 0 / p w m 6 p e . 1 / p w m 7 p e . 2 p e . 3 p e . 4 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 p s 2 _ d a t / p f . 2 p s 2 _ c l k / p f . 3 s p i 2 _ s s 0 / p d . 0 s p i 2 _ c l k / p d . 1 s p i 2 _ m i s o 0 / p d . 2 s p i 2 _ m o s i 0 / p d . 3 s p i 2 _ m i s o 1 / p d . 4 s p i 2 _ m o s i 1 / p d . 5 v r e f
n u m icro ? j an 31 , 201 9 page 19 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 3.2.1.2 numicro ? nuc 2 0 0 rxx an lqfp 64 - pin figure 3 - 3 numicro ? nuc 2 00 s xxan lqfp 64 - pin diagram a d c 5 / p a . 5 a d c 6 / p a . 6 v r e f i n t 0 / p b . 1 4 c m p 1 _ o / p b . 1 3 v b a t x 3 2 _ i n x 3 2 _ o u t i 2 c 1 _ s c l / p a . 1 1 i 2 c 1 _ s d a / p a . 1 0 i 2 c 0 _ s c l / p a . 9 i 2 c 0 _ s d a / p a . 8 u a r t 1 _ r x d / p b . 4 u a r t 1 _ t x d / p b . 5 u a r t 1 _ n r t s / p b . 6 u a r t 1 _ n c t s / p b . 7 l d o _ c a p v d d v s s c m p 0 _ n / p c . 7 s c 0 _ c d / c m p 0 _ p / p c . 6 c m p 1 _ n / p c . 1 5 c m p 1 _ p / p c . 1 4 t m 0 _ e x t / i n t 1 / p b . 1 5 x t 1 _ o u t / p f . 0 x t 1 _ i n / p f . 1 n r e s e t c l k o / t m 0 / s t a d c / p b . 8 p a . 4 / a d c 4 p a . 3 / a d c 3 / s c 0 _ d a t p a . 2 / a d c 2 / s c 0 _ c l k p a . 1 / a d c 1 / s c 0 _ r s t p a . 0 / a d c 0 / s c 0 _ p w r a v s s i c e _ c l k i c e _ d a t p a . 1 2 / p w m 0 / s c 2 _ d a t p a . 1 3 / p w m 1 / s c 2 _ c l k p a . 1 4 / p w m 2 / s c 2 _ r s t p a . 1 5 / p w m 3 / i 2 s _ m c l k / s c 2 _ p w r p c . 8 / s p i 1 _ s s 0 p c . 9 / s p i 1 _ c l k a v d d v s s v d d p v s s p c . 0 / s p i 0 _ s s 0 / i 2 s _ l r c k p c . 1 / s p i 0 _ c l k / i 2 s _ b c l k p c . 2 / s p i 0 _ m i s o 0 / i 2 s _ d i p c . 3 / s p i 0 _ m o s i 0 / i 2 s _ d o 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 p c . 1 0 / s p i 1 _ m i s o 0 p c . 1 1 / s p i 1 _ m o s i 0 p b . 9 / t m 1 p b . 1 0 / t m 2 p b . 1 1 / t m 3 / p w m 4 p e . 5 / t m 1 _ e x t / p w m 5 p d . 1 5 / u a r t 2 _ t x d p d . 1 4 / u a r t 2 _ r x d p d . 7 p d . 6 p b . 3 / u a r t 0 _ n c t s / t m 3 _ e x t / s c 2 _ c d p b . 2 / u a r t 0 _ n r t s / t m 2 _ e x t / c m p 0 _ o p b . 1 / u a r t 0 _ t x d p b . 0 / u a r t 0 _ r x d n u c 2 0 0 s x x a n l q f p 6 4 - p i n
n u m icro ? j an 31 , 201 9 page 20 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 3.2.1.3 numicro ? nuc 2 0 0 lxx an lqfp 48 - pin figure 3 - 4 numicro ? nuc 2 00 lxx an lqfp 48 - pin diagram a d c 5 / p a . 5 a d c 6 / p a . 6 v r e f v b a t x 3 2 _ i n x 3 2 _ o u t i 2 c 1 _ s c l / p a . 1 1 i 2 c 1 _ s d a / p a . 1 0 i 2 c 0 _ s c l / p a . 9 i 2 c 0 _ s d a / p a . 8 u a r t 1 _ r x d / p b . 4 u a r t 1 _ t x d / p b . 5 l d o _ c a p v d d v s s c m p 0 _ n / p c . 7 s c 0 _ c d / c m p 0 _ p / p c . 6 t m 0 _ e x t / i n t 1 / p b . 1 5 x t 1 _ o u t / p f . 0 x t 1 _ i n / p f . 1 n r e s e t c l k o / t m 0 / s t a d c / p b . 8 p a . 4 / a d c 4 p a . 3 / a d c 3 / s c 0 _ d a t p a . 2 / a d c 2 / s c 0 _ c l k p a . 1 / a d c 1 / s c 0 _ r s t p a . 0 / a d c 0 / s c 0 _ p w r a v s s i c e _ c l k i c e _ d a t p a . 1 2 / p w m 0 / s c 2 _ d a t p a . 1 3 / p w m 1 / s c 2 _ c l k p a . 1 4 / p w m 2 / s c 2 _ r s t p a . 1 5 / p w m 3 / i 2 s _ m c l k / s c 2 _ p w r a v d d p v s s p b . 9 / t m 1 p b . 1 0 / t m 2 p b . 1 1 / t m 3 / p w m 4 p e . 5 / t m 1 _ e x t / p w m 5 p b . 3 / u a r t 0 _ n c t s / t m 3 _ e x t / s c 2 _ c d p b . 2 / u a r t 0 _ n r t s / t m 2 _ e x t / c m p 0 _ o 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 n u c 2 0 0 l x x a n l q f p 4 8 - p i n p b . 1 / u a r t 0 _ t x d p b . 0 / u a r t 0 _ r x d p c . 0 / s p i 0 _ s s 0 / i 2 s _ l r c k p c . 1 / s p i 0 _ c l k / i 2 s _ b c l k p c . 2 / s p i 0 _ m i s o 0 / i 2 s _ d i p c . 3 / s p i 0 _ m o s i 0 / i 2 s _ d o
n u m icro ? j an 31 , 201 9 page 21 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 3.2.2 numicro ? 3.2.2.1 numicro ? nuc 2 20 vxx an lqfp 100 - pin figure 3 - 5 numicro ? nuc 2 20 vxx an lqfp 100 - pin diagram s c 1 _ r s t / a d c 5 / p a . 5 s c 1 _ c l k / a d c 6 / p a . 6 s c 1 _ d a t / a d c 7 / s p i 2 _ s s 1 / p a . 7 s p i 3 _ s s 1 / i n t 0 / p b . 1 4 c m p 1 _ o / p b . 1 3 v b a t x 3 2 _ i n x 3 2 _ o u t i 2 c 1 _ s c l / p a . 1 1 i 2 c 1 _ s d a / p a . 1 0 i 2 c 0 _ s c l / p a . 9 i 2 c 0 _ s d a / p a . 8 u a r t 1 _ r x d / p b . 4 u a r t 1 _ t x d / p b . 5 u a r t 1 _ n r t s / p b . 6 u a r t 1 _ n c t s / p b . 7 l d o _ c a p v d d v s s s c 1 _ c d / c m p 0 _ n / p c . 7 s c 0 _ c d / c m p 0 _ p / p c . 6 c m p 1 _ n / p c . 1 5 c m p 1 _ p / p c . 1 4 t m 0 _ e x t / i n t 1 / p b . 1 5 x t 1 _ o u t / p f . 0 x t 1 _ i n / p f . 1 n r e s e t c l k o / t m 0 / s t a d c / p b . 8 p a . 4 / a d c 4 / s c 1 _ p w r p a . 3 / a d c 3 / s c 0 _ d a t p a . 2 / a d c 2 / s c 0 _ c l k p a . 1 / a d c 1 / s c 0 _ r s t p a . 0 / a d c 0 / s c 0 _ p w r a v s s i c e _ c l k i c e _ d a t p a . 1 2 / p w m 0 / s c 2 _ d a t p a . 1 3 / p w m 1 / s c 2 _ c l k p a . 1 4 / p w m 2 / s c 2 _ r s t p a . 1 5 / p w m 3 / i 2 s _ m c l k / s c 2 _ p w r p c . 8 / s p i 1 _ s s 0 p c . 9 / s p i 1 _ c l k a v d d v s s v d d p v s s p c . 0 / s p i 0 _ s s 0 / i 2 s _ l r c k p c . 1 / s p i 0 _ c l k / i 2 s _ b c l k p c . 2 / s p i 0 _ m i s o 0 / i 2 s _ d i p c . 3 / s p i 0 _ m o s i 0 / i 2 s _ d o p d . 1 5 / u a r t 2 _ t x d p d . 1 4 / u a r t 2 _ r x d p d . 7 p d . 6 p b . 3 / u a r t 0 _ n c t s / t m 3 _ e x t / s c 2 _ c d p b . 2 / u a r t 0 _ n r t s / t m 2 _ e x t / c m p 0 _ o p b . 1 / u a r t 0 _ t x d p b . 0 / u a r t 0 _ r x d u s b _ d + u s b _ d - u s b _ v d d 3 3 _ c a p u s b _ v b u s 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 p c . 1 0 / s p i 1 _ m i s o 0 p c . 1 1 / s p i 1 _ m o s i 0 n u c 2 2 0 v x x a n l q f p 1 0 0 - p i n 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 p e . 1 5 p e . 1 4 p e . 1 3 s p i 3 _ s s 0 / p d . 8 s p i 3 _ c l k / p d . 9 s p i 3 _ m i s o 0 / p d . 1 0 s p i 3 _ m o s i 0 / p d . 1 1 s p i 3 _ m i s o 1 / p d . 1 2 s p i 3 _ m o s i 1 / p d . 1 3 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 p e . 7 p e . 8 p c . 4 / s p i 0 _ m i s o 1 p c . 5 / s p i 0 _ m o s i 1 p b . 9 / t m 1 / s p i 1 _ s s 1 p b . 1 0 / t m 2 / s p i 0 _ s s 1 p b . 1 1 / t m 3 / p w m 4 p e . 5 / t m 1 _ e x t / p w m 5 p e . 6 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 v s s v d d p c . 1 2 / s p i 1 _ m i s o 1 p c . 1 3 / s p i 1 _ m o s i 1 p e . 0 / p w m 6 p e . 1 / p w m 7 p e . 2 p e . 3 p e . 4 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 p s 2 _ d a t / p f . 2 p s 2 _ c l k / p f . 3 s p i 2 _ s s 0 / p d . 0 s p i 2 _ c l k / p d . 1 s p i 2 _ m i s o 0 / p d . 2 s p i 2 _ m o s i 0 / p d . 3 s p i 2 _ m i s o 1 / p d . 4 s p i 2 _ m o s i 1 / p d . 5 v r e f
n u m icro ? j an 31 , 201 9 page 22 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 3.2.2.2 numicro ? nuc 2 20 rxx an lqfp 64 - pin figure 3 - 6 numicro ? nuc 2 20 s xxan lqfp 64 - pin diagram a d c 5 / p a . 5 a d c 6 / p a . 6 v r e f i n t 0 / p b . 1 4 c m p 1 _ o / p b . 1 3 v b a t x 3 2 _ i n x 3 2 _ o u t i 2 c 1 _ s c l / p a . 1 1 i 2 c 1 _ s d a / p a . 1 0 i 2 c 0 _ s c l / p a . 9 i 2 c 0 _ s d a / p a . 8 u a r t 1 _ r x d / p b . 4 u a r t 1 _ t x d / p b . 5 u a r t 1 _ n r t s / p b . 6 u a r t 1 _ n c t s / p b . 7 l d o _ c a p v d d v s s c m p 0 _ n / p c . 7 s c 0 _ c d / c m p 0 _ p / p c . 6 c m p 1 _ n / p c . 1 5 c m p 1 _ p / p c . 1 4 t m 0 _ e x t / i n t 1 / p b . 1 5 x t 1 _ o u t / p f . 0 x t 1 _ i n / p f . 1 n r e s e t c l k o / t m 0 / s t a d c / p b . 8 p a . 4 / a d c 4 p a . 3 / a d c 3 / s c 0 _ d a t p a . 2 / a d c 2 / s c 0 _ c l k p a . 1 / a d c 1 / s c 0 _ r s t p a . 0 / a d c 0 / s c 0 _ p w r a v s s i c e _ c l k i c e _ d a t p a . 1 2 / p w m 0 / s c 2 _ d a t p a . 1 3 / p w m 1 / s c 2 _ c l k p a . 1 4 / p w m 2 / s c 2 _ r s t p a . 1 5 / p w m 3 / i 2 s _ m c l k / s c 2 _ p w r p c . 8 / s p i 1 _ s s 0 p c . 9 / s p i 1 _ c l k a v d d v s s v d d p v s s p c . 0 / s p i 0 _ s s 0 / i 2 s _ l r c k p c . 1 / s p i 0 _ c l k / i 2 s _ b c l k p c . 2 / s p i 0 _ m i s o 0 / i 2 s _ d i p c . 3 / s p i 0 _ m o s i 0 / i 2 s _ d o u s b _ d + u s b _ d - u s b _ v d d 3 3 _ c a p u s b _ v b u s 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 p c . 1 0 / s p i 1 _ m i s o 0 p c . 1 1 / s p i 1 _ m o s i 0 p b . 9 / t m 1 p b . 1 0 / t m 2 p b . 1 1 / t m 3 / p w m 4 p e . 5 / t m 1 _ e x t / p w m 5 p b . 3 / u a r t 0 _ n c t s / t m 3 _ e x t / s c 2 _ c d p b . 2 / u a r t 0 _ n r t s / t m 2 _ e x t / c m p 0 _ o p b . 1 / u a r t 0 _ t x d p b . 0 / u a r t 0 _ r x d n u c 2 2 0 s x x a n l q f p 6 4 - p i n
n u m icro ? j an 31 , 201 9 page 23 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 3.2.2.3 numicro ? nuc 2 20 lxx an lqfp 48 - pin figure 3 - 7 numicro ? nuc 2 20 lxx an lqfp 48 - pin diagram a d c 5 / p a . 5 a d c 6 / p a . 6 v r e f v b a t x 3 2 _ i n x 3 2 _ o u t i 2 c 1 _ s c l / p a . 1 1 i 2 c 1 _ s d a / p a . 1 0 i 2 c 0 _ s c l / p a . 9 i 2 c 0 _ s d a / p a . 8 u a r t 1 _ r x d / p b . 4 u a r t 1 _ t x d / p b . 5 l d o _ c a p v d d v s s c m p 0 _ n / p c . 7 s c 0 _ c d / c m p 0 _ p / p c . 6 t m 0 _ e x t / i n t 1 / p b . 1 5 x t 1 _ o u t / p f . 0 x t 1 _ i n / p f . 1 n r e s e t c l k o / t m 0 / s t a d c / p b . 8 p a . 4 / a d c 4 p a . 3 / a d c 3 / s c 0 _ d a t p a . 2 / a d c 2 / s c 0 _ c l k p a . 1 / a d c 1 / s c 0 _ r s t p a . 0 / a d c 0 / s c 0 _ p w r a v s s i c e _ c l k i c e _ d a t p a . 1 2 / p w m 0 / s c 2 _ d a t p a . 1 3 / p w m 1 / s c 2 _ c l k p a . 1 4 / p w m 2 / s c 2 _ r s t p a . 1 5 / p w m 3 / i 2 s _ m c l k / s c 2 _ p w r a v d d p v s s p c . 0 / s p i 0 _ s s 0 / i 2 s _ l r c k p c . 1 / s p i 0 _ c l k / i 2 s _ b c l k p c . 2 / s p i 0 _ m i s o 0 / i 2 s _ d i p c . 3 / s p i 0 _ m o s i 0 / i 2 s _ d o p b . 3 / u a r t 0 _ n c t s / t m 3 _ e x t / s c 2 _ c d p b . 2 / u a r t 0 _ n r t s / t m 2 _ e x t / c m p 0 _ o p b . 1 / u a r t 0 _ t x d p b . 0 / u a r t 0 _ r x d u s b _ d + u s b _ d - u s b _ v d d 3 3 _ c a p u s b _ v b u s 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 n u c 2 2 0 l x x a n l q f p 4 8 - p i n
n u m icro ? j an 31 , 201 9 page 24 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 3.3 pin description 3.3.1 numicro ? pin no. pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin 1 pe.15 i/o general purpose digital i/o pin . 2 pe.14 i/o general purpose digital i/o pin . 3 pe.13 i/o general purpose digital i/o pin . 4 1 pb.14 i/o general purpose digital i/o pin. int0 i external interrupt 0 input pin . spi3_ ss1 i/o 2 nd spi3 slave select pin . 5 2 pb.13 i/o general purpose digital i/o pin . c m p 1_ o o comparator1 output pin . 6 3 1 v bat p p ower supply by batteries for rtc . 7 4 2 x32 _ o ut o external 32.768 khz ( low speed ) crystal output pin . 8 5 3 x32 _ i n i external 32.768 khz ( low speed ) crystal input pin . 9 6 4 pa.11 i/o general purpose digital i/o pin . i2c1 _ scl i/o i 2 c 1 clock pin . 10 7 5 pa.10 i/o general purpose digital i/o pin. i2c1 _ sda i/o i 2 c 1 data input/output pin . 11 8 6 pa.9 i/o general purpose digital i/o pin. i2c0 _ scl i/o i 2 c0 clock pin . 12 9 7 pa.8 i/o general purpose digital i/o pin. i2c0 _ sda i/o i 2 c0 data input/output pin . 13 pd.8 i/o general purpose digital i/o pin . spi3_ ss 0 i/o 1 st spi3 slave select pin . 14 pd.9 i/o general purpose digital i/o pin . spi3_ clk i/o spi3 serial clock pin . 15 pd.10 i/o general purpose digital i/o pin . spi3_ miso 0 i/o 1 st spi3 miso (master in, slave out) pin . 16 pd.11 i/o general purpose digital i/o pin . spi3_ mosi 0 i/o 1 st spi3 mosi (master out, slave in) pin .
n u m icro ? j an 31 , 201 9 page 25 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet pin no. pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin 17 pd.12 i/o general purpose digital i/o pin . spi3_ miso 1 i/o 2 nd spi3 miso (master in, slave out) pin . 18 pd.13 i/o general purpose digital i/o pin . spi3_ mosi 1 i/o 2 nd spi3 mosi (master out, slave in) pin . 19 10 8 pb.4 i/o general purpose digital i/o pin . uart1_ rxd i data receiver input pin for uart1 . 20 11 9 pb.5 i/o general purpose digital i/o pin . uart1_ txd o data transmitter output pin for uart1 . 21 12 pb.6 i/o general purpose digital i/o pin . uart1_n rts o request to send output pin for uart1 . 22 13 pb.7 i/o general purpose digital i/o pin . uart1_n cts i clear to send input pin for uart1 . 23 14 10 ldo _cap p ldo output pin . 24 15 11 v dd p power supply for i/o ports and ld o source for internal pll and digital circuit . 25 16 12 v ss p ground pin for digital circuit. 26 pe. 12 i/o general purpose digital i/o pin . 27 pe. 11 i/o general purpose digital i/o pin . 28 pe. 10 i/o general purpose digital i/o pin . 29 pe. 9 i/o general purpose digital i/o pin . 30 pe.8 i/o general purpose digital i/o pin . 31 pe.7 i/o general purpose digital i/o pin . 32 17 13 pb.0 i/o general purpose digital i/o pin . uart0_ rxd i data receiver input pin for uart0 . 33 18 14 pb.1 i/o general purpose digital i/o pin . uart0_ txd o data transmitter output pin for uart0 . 34 19 15 pb.2 i/o general purpose digital i/o pin . uart0_n rts o request to send output pin for uart0 . t m 2 _ ex t i timer2 external capture input pin . c m p 0_ o o comparator0 output pin . 35 20 16 pb.3 i/o general purpose digital i/o pin.
n u m icro ? j an 31 , 201 9 page 26 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet pin no. pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin uart0_n cts i clear to send input pin for uart0 . t m 3 _ ex t i timer3 external capture input pin . sc2_cd i smartcard 2 card detect pin . 36 21 pd.6 i/o general purpose digital i/o pin . 37 22 pd.7 i/o general purpose digital i/o pin . 38 23 pd.14 i/o general purpose digital i/o pin . uart2_ rxd i data receiver input pin for uart2 . 39 24 pd.15 i/o general purpose digital i/o pin . uart2_ txd o data transmitter output pin for uart2 . 40 pc.5 i/o general purpose digital i/o pin . spi0_ mosi 1 i/o 2 nd spi 0 mosi (master out, slave in) pin . 41 pc.4 i/o general purpose digital i/o pin . spi0_ miso 1 i/o 2 nd spi 0 miso (master in, slave out) pin . 42 25 17 pc.3 i/o general purpose digital i/o pin . spi0_ mosi 0 i/o 1 st spi 0 mosi (master out, slave in) pin . i2s _ do o i 2 s data output . 43 26 18 pc.2 i/o general purpose digital i/o pin . spi0_ miso 0 i/o 1 st spi 0 miso (master in, slave out) pin . i2s _ di i i 2 s data input . 44 27 19 pc.1 i/o general purpose digital i/o pin . spi0_ clk i/o spi0 s erial clock pin . i2s _ bclk i/o i 2 s bit clock pin . 45 28 20 pc.0 i/o general purpose digital i/o pin . spi0_ ss 0 i/o 1 st spi0 slave select pin . i2s _ lrck i/o i 2 s left right channel clock . 46 pe.6 i/o general purpose digital i/o pin . 47 29 21 pe.5 i/o general purpose digital i/o pin . pwm 5 i/o pwm 5 output /capture input . t m 1 _ ex t i timer1 external capture input pin. 48 30 22 pb.11 i/o general purpose digital i/o pin .
n u m icro ? j an 31 , 201 9 page 27 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet pin no. pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin tm3 i/o timer3 event counter input / toggle output . pwm 4 i/o pwm 4 output /capture input . 49 31 23 pb.10 i/o general purpose digital i/o pin. tm2 i/o timer2 event counter input / toggle output . spi0_ ss 1 i/o 2 nd spi0 slave select pin . 50 32 24 pb.9 i/o general purpose digital i/o pin. tm1 i/o timer1 event counter input / toggle output . spi1_ ss 1 i/o 2 nd spi1 slave select pin . 51 pe.4 i/o general purpose digital i/o pin . 52 pe.3 i/o general purpose digital i/o pin . 53 pe.2 i/o general purpose digital i/o pin . 54 pe.1 i/o general purpose digital i/o pin . pwm 7 i/o pwm 7 output /capture input . 55 pe.0 i/o general purpose digital i/o pin . pwm 6 i/o pwm 6 output /capture input . 56 pc.13 i/o general purpose digital i/o pin . spi1_ mosi 1 i/o 2 nd spi 1 mosi (master out, slave in) pin . 57 pc.12 i/o general purpose digital i/o pin . spi1_ miso 1 i/o 2 nd spi 1 miso (master in, slave out) pin . 58 33 pc.11 i/o general purpose digital i/o pin . spi1_ mosi 0 i/o 1 st spi 1 mosi (master out, slave in) pin . 59 34 pc.10 i/o general purpose digital i/o pin . spi1_ miso 0 i/o 1 st spi 1 miso (master in, slave out) pin . 60 35 pc.9 i/o general purpose digital i/o pin . spi1_ clk i/o spi1 s erial clock pin . 61 36 pc.8 i/o general purpose digital i/o pin . spi1_ ss 0 i/o 1 st spi1 slave select pin . 62 37 25 pa.15 i/o general purpose digital i/o pin. pwm3 i/o pwm output /capture input . i2s _ mclk o i 2 s master clock output pin .
n u m icro ? j an 31 , 201 9 page 28 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet pin no. pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin sc2_pwr o smartcard 2 power pin . 63 38 26 pa.14 i/o general purpose digital i/o pin. pwm2 i/o pwm 2 output /capture input . sc2_rst o smartcard 2 reset pin . 64 39 27 pa.13 i/o general purpose digital i/o pin. pwm1 i/o pwm 1 output /capture input . sc2_clk o smartcard 2 clock pin . 65 40 28 pa.12 i/o general purpose digital i/o pin. pwm0 i/o pwm 0 output /capture input . sc2_dat o smartcard 2 data pin . 66 41 29 ice _ dat i/o serial w ire d ebu g ger d ata pin . 67 42 30 ice_c l k i serial w ire d ebu g ger c lock pin . 68 v dd p power supply for i/o ports and ld o source for internal pll and digital circuit. 69 v ss p ground pin for digital circuit. 70 43 31 av ss ap ground p in for analog circuit . 71 44 32 pa.0 i/o general purpose digital i/o pin. adc0 ai adc 0 analog input . sc0_pwr o smartcard 0 power pin . 72 45 33 pa.1 i/o general purpose digital i/o pin. adc1 ai adc 1 analog input . sc0_rst o smartcard 0 reset pin . 73 46 34 pa.2 i/o general purpose digital i/o pin. adc2 ai adc 2 analog input . sc0_clk o smartcard 0 clock pin . 74 47 35 pa.3 i/o general purpose digital i/o pin. adc3 ai adc 3 analog input . sc0_dat o smartcard 0 data pin . 75 48 36 pa. 4 i/o general purpose digital i/o pin. adc4 ai adc 4 analog input . sc1 _pwr o smartcard1 power pin .
n u m icro ? j an 31 , 201 9 page 29 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet pin no. pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin 76 49 37 pa.5 i/o general purpose digital i/o pin. adc5 ai adc 5 analog input . sc1 _rst o smartcard1 reset pin . 77 50 38 pa.6 i/o general purpose digital i/o pin. adc6 ai adc 6 analog input . sc1 _clk i/o smartcard1 clock pin . 78 pa.7 i/o general purpose digital i/o pin. adc7 ai adc 7 analog input . sc1 _dat o smartcard1 data pin . spi2_ ss1 i/o 2 nd spi2 slave select pin . 79 51 39 v ref ap v oltage reference input for adc . 80 52 40 av dd ap p ower supply for internal analog circuit . 81 pd.0 i/o general purpose digital i/o pin. spi2_ ss 0 i/o 1 st spi2 slave select pin . 82 pd.1 i/o general purpose digital i/o pin. spi2_ clk i/o spi2 s erial clock pin . 83 pd.2 i/o general purpose digital i/o pin. spi2_ miso 0 i/o 1 st spi 2 miso (master in, slave out) pin . 84 pd.3 i/o general purpose digital i/o pin. spi2_ mosi 0 i/o 1 st spi 2 mosi (master out, slave in) pin . 85 pd.4 i/o general purpose digital i/o pin. spi2_ miso 1 i/o 2 nd spi 2 miso (master in, slave out) pin . 86 pd.5 i/o general purpose digital i/o pin. spi2_ mosi 1 i/o 2 nd spi 2 mosi (master out, slave in) pin . 87 53 41 pc.7 i/o general purpose digital i/o pin. c m p 0_ n ai comparator 0 n egative input pin . sc1 _ cd i smartcard1 card detect pin . 88 54 42 pc.6 i/o general purpose digital i/o pin. c m p 0_ p ai comparator 0 p ositive input pin . sc 0_ cd i smartcard 0 card detect pin . 89 55 pc.15 i/o general purpose digital i/o pin.
n u m icro ? j an 31 , 201 9 page 30 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet pin no. pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin c m p 1_ n ai comparator 1 n egative input pin . 90 56 pc.14 i/o general purpose digital i/o pin. c m p 1_ p ai comparator1 p ositive input pin . 91 57 43 pb.15 i/o general purpose digital i/o pin. int1 i external interrupt 1 input pin . t m 0 _ ex t i timer0 external capture input pin. 92 58 44 pf.0 i/o general purpose digital i/o pin. xt 1 _out o external 4~24 mhz ( high speed ) crystal output pin . 93 59 45 pf.1 i/o general purpose digital i/o pin. xt 1 _in i external 4~24 mhz ( high speed ) crystal input pin . 94 60 46 n reset i external reset input : active low , with an internal pull - up . s et this pin low reset chip to initial state . 95 61 v ss p ground pin for digital circuit. 96 62 v dd p power supply for i/o ports and ld o source for internal pll and digital circuit. 97 pf.2 i/o general purpose digital i/o pin. ps2 _ dat i/o ps2 d ata pin . 98 pf.3 i/o general purpose digital i/o pin. ps2 _ clk i/o ps2 clock pin . 99 63 47 pv ss p pll ground . 100 64 48 pb.8 i/o general purpose digital i/o pin. stadc i adc external trigger input. tm0 i/o timer0 event counter input / toggle output . clko o frequency d ivider clock output pin . note: pin type i = digital input, o = digital output; ai = analog input; p = power pin; ap = analog power .
n u m icro ? j an 31 , 201 9 page 31 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 3.3.2 numicro ? pin no. pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin 1 pe.15 i/o general purpose digital i/o pin . 2 pe.14 i/o general purpose digital i/o pin . 3 pe.13 i/o general purpose digital i/o pin . 4 1 pb.14 i/o general purpose digital i/o pin . int0 i external interrupt 0 input pin . spi3_ ss1 i/o 2 nd spi3 slave select pin . 5 2 pb.13 i/o general purpose digital i/o pin . c m p 1_ o o comparator 1 output pin . 6 3 1 v bat p power supply by batteries for rtc. 7 4 2 x32 _ o ut o external 32.768 khz ( low speed ) crystal output pin . 8 5 3 x32 _ i n i external 32.768 khz ( low speed ) crystal input pin . 9 6 4 pa.11 i/o general purpose digital i/o pin . i2c1 _ scl i/o i 2 c 1 clock pin . 10 7 5 pa.10 i/o general purpose digital i/o pin . i2c1 _ sda i/o i 2 c 1 data input/output pin . 11 8 6 pa.9 i/o general purpose digital i/o pin . i2c0 _ scl i/o i 2 c0 clock pin . 12 9 7 pa.8 i/o general purpose digital i/o pin . i2c0 _ sda i/o i 2 c0 data input/output pin . 13 pd.8 i/o general purpose digital i/o pin . spi3_ ss 0 i/o 1 st spi3 slave select pin . 14 pd.9 i/o general purpose digital i/o pin . spi3_ clk i/o spi3 serial clock pin . 15 pd.10 i/o general purpose digital i/o pin . spi3_ miso 0 i/o 1 st spi3 miso (master in, slave out) pin . 16 pd.11 i/o general purpose digital i/o pin . spi3_ mosi 0 i/o 1 st spi3 mosi (master out, slave in) pin . 17 pd.12 i/o general purpose digital i/o pin . spi3_ miso 1 i/o 2 nd spi3 miso (master in, slave out) pin . 18 pd.13 i/o general purpose digital i/o pin .
n u m icro ? j an 31 , 201 9 page 32 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet pin no. pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin spi3_ mosi 1 i/o 2 nd spi3 mosi (master out, slave in) pin . 19 10 8 pb.4 i/o general purpose digital i/o pin . uart1_ rxd i data receiver input pin for uart1 . 20 11 9 pb.5 i/o general purpose digital i/o pin . uart1_ txd o data transmitter output pin for uart1 . 21 12 pb.6 i/o general purpose digital i/o pin . uart1_n rts o request to send output pin for uart1 . 22 13 pb.7 i/o general purpose digital i/o pin . uart1_n cts i clear to send input pin for uart1 . 23 14 10 ldo _cap p ldo output pin . 24 15 11 v dd p power supply for i/o ports and ld o source for internal pll and digital circuit. 25 16 12 v ss p ground pin for digital circuit. 26 pe.8 i/o general purpose digital i/o pin . 27 pe.7 i/o general purpose digital i/o pin . 28 17 13 usb_ v bus usb power supply from usb host or hub . 29 18 14 usb_ v dd33_ cap usb internal power regulator output 3.3v decoupling pin. 30 19 15 usb_ d - usb usb d ifferential s ignal d - . 31 20 16 usb_ d+ usb usb d ifferential s ignal d+ . 32 21 17 pb.0 i/o general purpose digital i/o pin . uart0_ rxd i data receiver input pin for uart0 . 33 22 18 pb.1 i/o general purpose digital i/o pin . uart0_ txd o data transmitter output pin for uart0 . 34 23 19 pb.2 i/o general purpose digital i/o pin . uart0_n rts o request to send output pin for uart0 . t m 2 _ ex t i timer2 external capture input pin . c m p 0_ o o comparator0 output pin . 35 24 20 pb.3 i/o general purpose digital i/o pin . uart0_n cts i clear to send input pin for uart0 . t m 3 _ ex t i timer3 external capture input pin . sc2_cd i smartcard 2 card detect pin .
n u m icro ? j an 31 , 201 9 page 33 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet pin no. pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin 36 pd.6 i/o general purpose digital i/o pin . 37 pd.7 i/o general purpose digital i/o pin . 38 pd.14 i/o general purpose digital i/o pin . uart2_ rxd i data receiver input pin for uart2 . 39 pd.15 i/o general purpose digital i/o pin . uart2_ txd o data transmitter output pin for uart2 . 40 pc.5 i/o general purpose digital i/o pin . spi0_ mosi 1 i/o 2 nd spi 0 mosi (master out, slave in) pin . 41 pc.4 i/o general purpose digital i/o pin . spi0_ miso 1 i/o 2 nd spi 0 miso (master in, slave out) pin . 42 25 21 pc.3 i/o general purpose digital i/o pin . spi0_ mosi 0 i/o 1 st spi 0 mosi (master out, slave in) pin . i2s _ do o i 2 s data output . 43 26 22 pc.2 i/o general purpose digital i/o pin . spi0_ miso 0 i/o 1 st spi 0 miso (master in, slave out) pin . i2s _ di i i 2 s data input . 44 27 23 pc.1 i/o general purpose digital i/o pin . spi0_ clk i/o spi0 s erial clock pin . i2s _ bclk i/o i 2 s bit clock pin . 45 28 24 pc.0 i/o general purpose digital i/o pin . spi0_ ss 0 i/o 1 st spi0 slave select pin . i2s _ lrck i/o i 2 s left right channel clock . 46 pe.6 i/o general purpose digital i/o pin . 47 29 pe.5 i/o general purpose digital i/o pin . pwm 5 i/o pwm 5 output /capture input . t m 1 _ ex t i timer1 external capture input pin . 48 30 pb.11 i/o general purpose digital i/o pin . tm3 i/o timer3 event counter input / toggle output . pwm 4 i/o pwm 4 output /capture input . 49 31 pb.10 i/o general purpose digital i/o pin .
n u m icro ? j an 31 , 201 9 page 34 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet pin no. pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin tm2 i/o timer2 event counter input / toggle output . spi0_ ss 1 i/o 2 nd spi0 slave select pin . 50 32 pb.9 i/o general purpose digital i/o pin . tm1 i/o timer1 event counter input / toggle output . spi1_ ss 1 i/o 2 nd spi1 slave select pin . 51 pe.4 i/o general purpose digital i/o pin . 52 pe.3 i/o general purpose digital i/o pin . 53 pe.2 i/o general purpose digital i/o pin . 54 pe.1 i/o general purpose digital i/o pin . pwm 7 i/o pwm 7 output /capture input . 55 pe.0 i/o general purpose digital i/o pin . pwm 6 i/o pwm 6 output /capture input . 56 pc.13 i/o general purpose digital i/o pin . spi1_ mosi 1 i/o 2 nd spi 1mosi (master out, slave in) pin . 57 pc.12 i/o general purpose digital i/o pin . spi1_ miso 1 i/o 2 nd spi 1 miso (master in, slave out) pin . 58 33 pc.11 i/o general purpose digital i/o pin . spi1_ mosi 0 i/o 1 st spi 1 mosi (master out, slave in) pin . 59 34 pc.10 i/o general purpose digital i/o pin . spi1_ miso 0 i/o 1 st spi 1 miso (master in, slave out) pin . 60 35 pc.9 i/o general purpose digital i/o pin . spi1_ clk i/o spi1 s erial clock pin . 61 36 pc.8 i/o general purpose digital i/o pin . spi1_ ss 0 i/o 1 st spi1 slave select pin . 62 37 25 pa.15 i/o general purpose digital i/o pin . pwm3 i/o pwm 3 output /capture input . i2s _ mclk o i 2 s master clock output pin . sc2_pwr o smartcard 2 power pin . 63 38 26 pa.14 i/o general purpose digital i/o pin . pwm2 i/o pwm 2 output /capture input . sc2_rst o smartcard 2 reset pin .
n u m icro ? j an 31 , 201 9 page 35 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet pin no. pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin 64 39 27 pa.13 i/o general purpose digital i/o pin . pwm1 i/o pwm 1 output /capture input . sc2_clk o smartcard 2 clock pin . 65 40 28 pa.12 i/o general purpose digital i/o pin . pwm0 i/o pwm 0 output /capture input . sc2_dat o smartcard 2 data pin . 66 41 29 ice _ dat i/o serial w ire d ebu g ger d ata pin . 67 42 30 ice_c l k i serial w ire d ebu g ger c lock pin . 68 v dd p power supply for i/o ports and ld o source for internal pll and digital circuit. 69 v ss p ground pin for digital circuit. 70 43 31 av ss ap ground p in for analog circuit . 71 44 32 pa.0 i/o general purpose digital i/o pin . adc0 ai adc 0 analog input . sc0_pwr o smartcard 0 power pin . 72 45 33 pa.1 i/o general purpose digital i/o pin . adc1 ai adc 1 analog input . sc0_rst o smartcard 0 reset pin . 73 46 34 pa.2 i/o general purpose digital i/o pin . adc2 ai adc 2 analog input . sc0_clk o smartcard 0 clock pin . 74 47 35 pa.3 i/o general purpose digital i/o pin . adc3 ai adc 3 analog input . sc0_dat o smartcard 0 data pin . 75 48 36 pa. 4 i/o general purpose digital i/o pin . adc4 ai adc 4 analog input . sc1 _pwr o smartcard1 power pin . 76 49 37 pa.5 i/o general purpose digital i/o pin . adc5 ai adc 5 analog input . sc1 _rst o smartcard1 reset pin . 77 50 38 pa.6 i/o general purpose digital i/o pin .
n u m icro ? j an 31 , 201 9 page 36 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet pin no. pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin adc6 ai adc 6 analog input . sc1 _clk i/o smartcard1 clock pin . 78 pa.7 i/o general purpose digital i/o pin . adc7 ai adc 7 analog input . sc1 _ clk o smartcard1 clock pin . spi2_ ss1 i/o 2 nd spi2 slave select pin . 79 51 39 v ref ap v oltage reference input for adc . 80 52 40 av dd ap p ower supply for internal analog circuit . 81 pd.0 i/o general purpose digital i/o pin . spi2_ ss 0 i/o 1 st spi2 slave select pin . 82 pd.1 i/o general purpose digital i/o pin . spi2_ clk i/o spi2 s erial clock pin . 83 pd.2 i/o general purpose digital i/o pin . spi2_ miso 0 i/o 1 st spi 2 miso (master in, slave out) pin . 84 pd.3 i/o general purpose digital i/o pin . spi2_ mosi 0 i/o 1 st spi 2 mosi (master out, slave in) pin . 85 pd.4 i/o general purpose digital i/o pin . spi2_ miso 1 i/o 2 nd spi 2 miso (master in, slave out) pin . 86 pd.5 i/o general purpose digital i/o pin . spi2_ mosi 1 i/o 2 nd spi 2 mosi (master out, slave in) pin . 87 53 41 pc.7 i/o general purpose digital i/o pin . c m p 0_ n ai comparator 0 n egative input pin . sc1 _ cd i smartcard1 card detect pin . 88 54 42 pc.6 i/o general purpose digital i/o pin . c m p 0_ p ai comparator 0 p ositive input pin . sc 0_ cd i smartcard 0 card detect pin . 89 55 pc.15 i/o general purpose digital i/o pin . c m p 1_ n ai comparator1 n egative input pin . 90 56 pc.14 i/o general purpose digital i/o pin . c m p 1_ p ai comparator1 p ositive input pin . 91 57 43 pb.15 i/o general purpose digital i/o pin .
n u m icro ? j an 31 , 201 9 page 37 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet pin no. pin name pin type description lqfp 100 - pin lqfp 64 - pin lqfp 48 - pin int1 i external interrupt 1 input pin . t m 0 _ ex t i timer 0 external capture input pin . 92 58 44 pf.0 i/o general purpose digital i/o pin . xt 1 _out o external 4~24 mhz ( high speed ) crystal output pin . 93 59 45 pf.1 i/o general purpose digital i/o pin . xt 1 _in i external 4~24 mhz ( high speed ) crystal input pin . 94 60 46 n reset i external reset input : active low , with an internal pull - up . s et this pin low reset chip to initial state . 95 61 v ss p ground pin for digital circuit. 96 62 v dd p power supply for i/o ports and ld o source for internal pll and digital circuit. 97 pf.2 i/o general purpose digital i/o pin . ps2 _ dat i/o ps2 d ata pin . 98 pf.3 i/o general purpose digital i/o pin . ps2 _ clk i/o ps2 clock pin . 99 63 47 pv ss p pll ground . 100 64 48 pb.8 i/o general purpose digital i/o pin . stadc i adc external trigger input. tm0 i/o timer0 event counter input / toggle output . clko o frequency d ivider clock output pin . note: pin type i = digital input, o = digital output; ai = analog input; p = power pin; ap = analog power .
n u m icro ? j an 31 , 201 9 page 38 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 4 block diagram 4.1 numicro ? figure 4 - 1 numicro ? nuc2 0 0 block diagram a r m c o r t e x - m 0 5 0 m h z m e m o r y p d m a a p r o m 1 2 8 / 6 4 / 3 2 k b d a t a f l a s h 4 k b s r a m 1 6 / 8 k b t i m e r / p w m a n a l o g i n t e r f a c e 3 2 - b i t t i m e r x 4 r t c p w m / c a p t u r e t i m e r x 8 w a t c h d o g t i m e r 1 2 - b i t a d c x 8 p o w e r c o n t r o l c l o c k c o n t r o l l d o p o w e r o n r e s e t l v r b r o w n o u t d e t e c t i o n h i g h s p e e d o s c i l l a t o r 2 2 . 1 1 8 4 m h z h i g h s p e e d c r y s t a l o s c . 4 ~ 2 4 m h z l o w s p e e d o s c i l l a t o r 1 0 k h z p l l c o n n e c t i v i t y u a r t x 3 s p i x 4 i 2 c x 2 p s / 2 i 2 s s c x 3 i / o p o r t s g e n e r a l p u r p o s e i / o r e s e t p i n e x t e r n a l i n t e r r u p t a n a l o g c o m p a r a t o r x 2 l o w s p e e d c r y s t a l o s c . 3 2 . 7 6 8 k h z l d r o m 4 k b a h b b u s a p b b u s b r i d g e
n u m icro ? j an 31 , 201 9 page 39 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 4.2 numicro ? figure 4 - 2 numicro ? nuc2 2 0 block diagram a r m c o r t e x - m 0 5 0 m h z m e m o r y a p r o m 1 2 8 / 6 4 / 3 2 k b d a t a f l a s h 4 k b s r a m 1 6 / 8 k b t i m e r / p w m a n a l o g i n t e r f a c e 3 2 - b i t t i m e r x 4 r t c p w m / c a p t u r e t i m e r x 8 w a t c h d o g t i m e r 1 2 - b i t a d c x 8 p o w e r c o n t r o l c l o c k c o n t r o l l d o p o w e r o n r e s e t l v r b r o w n o u t d e t e c t i o n h i g h s p e e d o s c i l l a t o r 2 2 . 1 1 8 4 m h z h i g h s p e e d c r y s t a l o s c . 4 ~ 2 4 m h z l o w s p e e d o s c i l l a t o r 1 0 k h z p l l c o n n e c t i v i t y u a r t x 3 s p i x 4 i 2 c x 2 p s / 2 i 2 s s c x 3 i / o p o r t s g e n e r a l p u r p o s e i / o r e s e t p i n e x t e r n a l i n t e r r u p t a n a l o g c o m p a r a t o r x 2 l o w s p e e d c r y s t a l o s c . 3 2 . 7 6 8 k h z u s b l d r o m 4 k b u s b p h y a h b b u s a p b b u s b r i d g e p d m a
n u m icro ? j an 31 , 201 9 page 40 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5 functional d escription 5.1 arm ? cortex? - m0 core the cortex? - m0 processor is a configurable, multistage, 32 - bit r isc processor , which has an amba ah b - lite interface and includes an nvic component. it also has optional hardware debug functionality. the processor can execute thumb code and is compatible with other cortex? - m profile processor. the profile supports two modes - thread mode and handler mode. handler mode is entered as a result of an exception. an exception return can only be issued in handler mode. thread mode is entered on reset, and can be entered as a result of an exception return. figure 5 - 1 shows the functional controller of processor. figure 5 - 1 functional controller diagram t he implemented device provides the following components and features : ? a low gate count processor: ? armv6 - m thumb ? instruction set ? thumb - 2 technology ? armv6 - m compliant 24 - bit systick timer ? a 32 - bit hardware multiplier ? s ystem interface supported with little - endian data accesses ? a b ility to have deterministic, fi xed - latency, interrupt handling ? load/store - multiples and multicycle - multiplies that can be abandoned and restarted to faci litate rapid interrupt handling ? c application binary interface compliant exception model. this is the a rmv6 - m, c application binary interface (c - abi) compliant exception model that enables the use of pure c functions as interrupt handlers ? low p ower s leep mode entry using wait for interrupt (wfi), wait for even t (wfe) instructions, or the return from interrupt sleep - on - exit feature ? nvic: c o r t e x t m - m 0 p r o c e s s o r c o r e n e s t e d v e c t o r e d i n t e r r u p t c o n t r o l l e r ( n v i c ) b r e a k p o i n t a n d w a t c h p o i n t u n i t d e b u g g e r i n t e r f a c e b u s m a t r i x d e b u g a c c e s s p o r t ( d a p ) d e b u g c o r t e x t m - m 0 p r o c e s s o r c o r t e x t m - m 0 c o m p o n e n t s w a k e - u p i n t e r r u p t c o n t r o l l e r ( w i c ) i n t e r r u p t s s e r i a l w i r e o r j t a g d e b u g p o r t a h b - l i t e i n t e r f a c e
n u m icro ? j an 31 , 201 9 page 41 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet ? 32 external interrupt inputs, each with four levels of priority ? dedicated non - m askable interrupt (nmi) input ? support s for both level - sensitive and pulse - sensitive interrupt lines ? suppo rts wake - up interrupt controller (wic) and , providing u ltra - low p ower s leep mode ? d ebug support : ? four hardware breakpoints ? two watchpoints ? program counter sampling register (pcsr) for non - intrusive code profiling ? single step and vector catch capabilities ? bus interfaces: ? single 32 - bit amba - 3 ahb - lite system interface that provides simple integration to all system peripherals and memory ? single 32 - bit slave port that supports the dap (debug access port) .
n u m icro ? j an 31 , 201 9 page 42 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.2 system manager 5.2.1 overview system management includes th e following sections: ? system resets ? system memory map ? system management registers for part number id, chip reset and on - chip controllers reset , multi - functional pin control ? system timer (systick) ? nested vectored interrupt controller (nvic) ? system control registers 5.2.2 system reset the system reset can be issued by one of the following listed events . for these reset event flags can be read by rst s rc register. ? power - o n reset ? l ow level on the n reset pin ? watchdog time - out reset ? low voltage reset ? brown - out detect or reset ? cpu reset ? system reset system reset and power - o n reset all reset the whole chip including all peripherals. the difference between system reset and power - o n reset is external c rystal circuit and ispcon . bs bit. system reset does not reset external c ry stal circuit and ispcon . bs bit, but power - o n reset does.
n u m icro ? j an 31 , 201 9 page 43 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.2.3 system power distribution in this chip , the power distribution is divided into four segments. ? analog power from av dd and av ss provides the power for analog components operation. ? digital power from v dd and v ss supplies the power to the internal regulator which provides a fixed 1.8 v power for digital operation and i/o pins. ? usb transceiver power from usb_ v bus offers the power for operating the usb transceiver. ? battery power from v bat supplies the rtc and external 32.768 khz crystal . the outputs of internal voltage regulators, ldo _cap and usb_ v dd33_cap , require an external capacitor which should be located close to the corresponding pin. analog power (av dd ) should be the same voltage level of the digital power (v dd ). figure 5 - 2 shows the power distribution of numicro ? nuc 2 0 0 ; figure 5 - 3 shows the power distribution of numicro ? nuc 2 2 0 . figure 5 - 2 numicro ? nuc 2 0 0 power distribution diagram 1 2 - b i t s a r - a d c b r o w n - o u t d e t e c t o r l o w v o l t a g e r e s e t a n a l o g c o m p a r a t o r t e m p e r a t u r e s e n e o r f l a s h d i g i t a l l o g i c i n t e r n a l 2 2 . 1 1 8 4 m h z & 1 0 k h z o s c i l l a t o r a v d d a v s s l d o _ c a p 1 u f g p i o n u c 2 0 0 p o w e r d i s t r i b u t i o n l d o p l l p o r 5 0 p o r 1 8 e x t e r n a l 3 2 . 7 6 8 k h z c r y s t a l v d d v s s i o c e l l x 3 2 _ u t o x 3 2 _ i n p v s s v b a t r t c u l d o 1 . 8 v 1 . 8 v
n u m icro ? j an 31 , 201 9 page 44 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet figure 5 - 3 numicro ? nuc2 2 0 power distribution diagram l d o u s b 1 . 1 t r a n c e i v e r 5 v t o 3 . 3 v l d o p l l 1 2 - b i t s a r - a d c b r o w n - o u t d e t e c t o r p o r 5 0 p o r 1 8 l o w v o l t a g e r e s e t e x t e r n a l 3 2 . 7 6 8 k h z c r y s t a l a n a l o g c o m p a r a t o r t e m p e r a t u r e s e n e o r f l a s h d i g i t a l l o g i c 3 . 3 v 1 . 8 v i n t e r n a l 2 2 . 1 1 8 4 m h z & 1 0 k h z o s c i l l a t o r a v d d a v s s v d d v s s u s b _ v b u s u s b _ v d d 3 3 _ c a p u s b _ d + u s b _ d - l d o _ c a p 1 u f 1 u f i o c e l l g p i o x 3 2 _ o u t x 3 2 _ i n p v s s n u c 2 2 0 p o w e r d i s t r i b u t i o n v b a t r t c u l d o 1 . 8 v
n u m icro ? j an 31 , 201 9 page 45 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.2.4 system memory map the numicro ? nuc 2 00 series provides 4g - byte address ing space. the memory locations assigned to each on - chip controllers are shown in the following table. the detailed register definition, memory space, and programming detailed will be described in the following sections for each on - chip peripheral . the numicro ? nuc 2 00 series only supports little - endian data format. address space token controllers flash and sram memory space 0x0000_0000 C 0x0001_ffff flash_ba flash memory space (128 kb) 0x2000_0000 C 0x2000_3fff sram_ba sram memory space (16 kb) ahb controllers space (0x5000_0000 C 0x501f_ffff) 0x5000_0000 C 0x5000_01ff gcr_ba system global control registers 0x5000_0200 C 0x5000_02ff clk_ba clock control registers 0x5000_0300 C 0x5000_03ff int_ba interrupt multiplexer control registers 0x5000_4000 C 0x5000_7fff gpio_ba gpio control registers 0x5000_8000 C 0x5000_bfff pdma_ba peripheral dma control registers 0x5000_c000 C 0x5000_ffff fmc_ba flash memory control registers apb1 controllers space (0x4000_0000 ~ 0x400f_ffff) 0x4000_4000 C 0x4000_7fff wdt_ba watchdog timer control registers 0x4000_8000 C 0x4000_bfff rtc_ba real time clock (rtc) control register 0x4001_0000 C 0x4001_3fff tmr0 1 _ba timer0 /timer1 control registers 0x4002_0000 C 0x4002_3fff i2c0_ba i 2 c0 interface control registers 0x4003_0000 C 0x4003_3fff spi0_ba spi0 with master/slave function control registers 0x4003_4000 C 0x4003_7fff spi 1 _ba spi 1 with master/slave function control registers 0x4004_0000 C 0x4004_3fff pwma_ba pwm0 /1/2/3 control registers 0x4005_0000 C 0x4005_3fff uart0_ba uart0 control registers 0x4006_0000 C 0x4006_3fff usbd_ba usb 2.0 fs device controller registers 0x400d_0000 C 0x400d_3fff acmp_ba analog comparator control registers 0x400e_0000 C 0x400e_ffff adc_ba analog - digital - converter (adc) control registers apb2 controllers space (0x4010_0000 ~ 0x401f_ffff) 0x4010_0000 C 0x4010_3fff ps2_ba ps / 2 interface control registers
n u m icro ? j an 31 , 201 9 page 46 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 0x4011_0000 C 0x4011_3fff tmr2 3 _ba timer2 /timer3 control registers 0x4012_0000 C 0x4012_3fff i2c1_ba i 2 c1 interface control registers 0x4013_0000 C 0x4013_3fff spi 2 _ba spi 2 with master/slave function control r egisters 0x4013_4000 C 0x4013_7fff spi 3 _ba spi3 with master/s lave function control registers 0x40 1 4_0000 C 0x40 1 4_3fff pwmb_ba pwm 4/5/6/7 control regi sters 0x4015_0000 C 0x4015_3fff uart1_ba uart1 control registers 0x4015_ 4 000 C 0x4015_ 7 fff uart 2 _ba uart 2 control registers 0x40 19 _0000 C 0x40 19 _3fff sc 0_ba sc 0 control registers 0x40 19 _ 4 000 C 0x40 19 _ 7 fff sc1 _ba sc1 control registers 0x40 19 _ 8 000 C 0x40 19 _ b fff sc2 _ba sc2 control registers 0x40 1 a_0000 C 0x40 1 a_3fff i2s_ba i 2 s interface control registers system controllers space (0x e000 _ e 000 ~ 0x e000 _ e fff) 0x e000 _ e 0 1 0 C 0x e000 _ e0 ff syst _ba system timer control registers 0x e000 _ e10 0 C 0x e000 _ ec ff nvic _ba external interrupt controller control registers 0x e000 _ ed0 0 C 0x e000 _ ed8 f scs_ba system control registers table 5 - 1 address space assignments for on - chip controllers
n u m icro ? j an 31 , 201 9 page 47 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.2.5 system timer (systick) the cortex? - m0 includes an integrated system timer, systick , which provides a simple, 24 - bit clear - on - write, decrementing, wrap - on - zero counter with a flexible control mechanism. the counter can be used as a real time operating system (rtos) tick timer or as a simple counter. when system timer is enabled, it will count down from the value in the systick current value register (syst_cvr) to 0 , and reload (wrap) to the value in the systick reload value register (syst_rvr) on the next clock cycle , then decrement o n subsequent clocks. when the counter transitions to 0 , the countflag status bit is set. the countflag bit clears on reads. the syst_cvr value is unknown on reset. software should write to the register to clear it to 0 before enabling the feature. this ens ures the timer will count from the syst_rvr value rather than an arbitrary value when it is enabled. if the syst_rvr is 0 , the timer will be maintained with a current value of 0 after it is reloaded with this value. this mechanism can be used to disable the feature independently from the timer enable bit. for more detailed information, please refer to the arm ? cortex? - m0 technical reference manual and arm ? v6 - m architecture reference manual.
n u m icro ? j an 31 , 201 9 page 48 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.2.6 nested vectored interrupt controller (nvic) the cortex? - m0 provides an interrupt controller as an integral part of the exception mode, named as nested vectored interrupt controller (nvic) , which is closely coupled to the processor kernel and provides following features: ? nested and vectored interrupt support ? aut omatic processor state saving and restoration ? reduced and deterministic interrupt latency the nvic prioritizes and handles all supported exceptions. all exceptions are handled in handler mode. this nvic architecture supports 32 (irq[31:0]) discrete inter rupts with 4 levels of priority. all of the interrupts and most of the system exceptions can be configured to different priority levels. when an interrupt occurs, the nvic will compare the priority of the new interrupt to the current running ones priority . if the priority of the new interrupt is higher than the current one, the new interrupt handler will override the current handler. when a n interrupt is accepted, the starting address of the interrupt service routine (isr) is fetched from a vector table in memory. there is no need to determine which interrupt is accepted and branch to the starting address of the correlated isr by software. while the starting address is fetched, nvic will also automatically save processor state including the registers pc, p sr, lr, r0~r3, r12 to the stack. at the end of the isr, the nvic will restore the mentioned registers from stack and resume the normal execution. thus it will take less and deterministic time to process the interrupt request. the nvic supports tail chain ing which handles back - to - back interrupts efficiently without the overhead of states saving and restoration and therefore reduces delay time in switching to pending isr at the end of current isr. the nvic also supports late arrival which improves the ef ficiency of concurrent isrs. when a higher priority interrupt request occurs before the current isr starts to execute (at the stage of state saving and starting address fetching), the nvic will give priority to the higher one without delay penalty. thus it advances the real - time capability. for more detailed information, please refer to the arm ? cortex? - m0 technical reference manual and arm ? v6 - m architecture reference manual.
n u m icro ? j an 31 , 201 9 page 49 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.2.6.1 exception model and system interrupt map the following table lists the exce ption model supported by numicro ? nuc 2 00 series . software can set four levels of priority on some of these exceptions as well as on all interrupts. the highest user - configurable priority is denoted as 0 and the lowest priority is denoted as 3. the defa ult priority of all the user - configurable interrupts is 0. note that priority 0 is treated as the fourth priority on the system, after three system exceptions reset, nmi and hard fault. exception name vector number priority reset 1 - 3 nmi 2 - 2 hard fault 3 - 1 reserved 4 ~ 10 reserved svcall 11 configurable reserved 12 ~ 13 reserved pendsv 14 configurable systick 15 configurable interrupt (irq0 ~ irq31) 16 ~ 47 configurable table 5 - 2 exception model vector number interrupt number (bit in interrupt registers) interrupt name source ip interrupt d escription 0 ~ 15 - - - system exceptions 16 0 bod_ int brown - out brown - out low voltage detected interrupt 17 1 wdt_int wdt watchdog timer interrupt 18 2 eint0 gpio external signal interrupt from pb.14 pin 19 3 eint1 gpio external signal interrupt from pb.15 pin 20 4 gpab_int gpio external signal interrupt from p a[15:0] / p b[1 3 : 0 ] 21 5 gpcde f _int gpio external interrupt from p c [15:0] / p d [15:0] / p e [15:0] / pf[3:0] 22 6 pwma_int pwm 0~3 pwm0 , pwm1, pwm2 and pwm 3 interrupt 23 7 pwmb_int pwm 4~7 pwm4, pwm5, pwm6 and pwm7 interrupt 24 8 tmr0_int tmr0 timer 0 interrupt 25 9 tmr1_int tmr1 timer 1 interrupt 26 10 tmr2_int tmr2 timer 2 interrupt 27 11 tmr3_int tmr3 timer 3 interrupt
n u m icro ? j an 31 , 201 9 page 50 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 28 12 uart0 2 _int uart0 /2 uart0 and uart2 interrupt 29 13 uart1_int uart1 uart1 interrupt 30 14 spi0_int spi0 spi0 interrupt 31 15 spi1_int spi1 spi1 interrupt 32 16 spi2_int spi2 spi2 interrupt 33 17 spi3_int spi3 spi3 interrupt 34 18 i2c0_int i 2 c0 i 2 c0 interrupt 35 19 i2c1_int i 2 c1 i 2 c1 interrupt 36 20 reserved - - 37 21 reserved - - 38 22 sc01 2 _int sc0/1 /2 sc0 , sc1 and sc2 interrupt 39 23 usb_int usbd usb 2.0 fs device interrupt 40 24 ps2_int ps / 2 ps / 2 interrupt 41 25 acmp_int a cmp analog comparator - 0 or comaprator - 1 interrupt 42 26 pdma_int pdma pdma interrupt 43 27 i2s_int i 2 s i 2 s interrupt 44 28 pwrwu_int clkc clock controller interrupt for chip wake - up from power - down state 45 29 adc_int adc adc interrupt 46 30 irc t _int irc irc trim interrupt 47 31 rtc_int rtc real t ime c lock interrupt table 5 - 3 system interrupt map
n u m icro ? j an 31 , 201 9 page 51 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.2.6.2 vector table when an interrupt is accepted, the processor will automatically fetch the starting address of the interrupt service routine (isr) from a vector table in memory. for armv6 - m, the vector table base address is fixed at 0x00000000. the vector table contains the initialization value for the stack pointer on re set, and the entry point addresses for all exception handlers. the vector number on previous page defines the order of entries in the vector table associated with exception handler entry as illustrated in previous section. vector table word offset description 0 sp_main C the main stack pointer vector number exception entry pointer using that vector number table 5 - 4 vector table format 5.2.6.3 operation description nvic interrupts can be enabled and disabled by writing to their corresponding interrupt set - enable or interrupt clear - enable register bit - field. the registers use a write - 1 - to - enable and write - 1 - to - clear policy, both registers reading back the current enab led state of the corresponding interrupts. when an interrupt is disabled, interrupt assertion will cause the interrupt to become pending, however, the interrupt will not be activate d . if an interrupt is active when it is disabled, it remains in its active state until cleared by reset or an exception return. clearing the enable bit prevents new activations of the associated interrupt. nvic interrupts can be pended/un - pended using a complementary pair of registers to those used to enable/disable the interrupt s, named the set - pending register and clear - pending register respectively. the registers use a write - 1 - to - enable and write - 1 - to - clear policy, both registers reading back the current pended state of the corresponding interrupts. the clear - pending register h as no effect on the execution status of an active interrupt. nvic interrupts are prioritized by updating an 8 - bit field within a 32 - bit register (each register supporting four interrupts). the general registers associated with the nvic are all accessible f rom a block of memory in the system control space and will be described in next section.
n u m icro ? j an 31 , 201 9 page 52 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.2.6.4 interrupt source register map besides the interrupt control registers associated with the nvic, the numicro ? nuc 2 00 series also implement s some specific control registers to facilitate the interrupt functions, including interrupt source identification , nmi source selection and interrupt test mode , which are described below. r : read only, w : write only, r/w : both read and write register offset r/w description reset value int base address: int_ba = 0x5000_0300 irq0_src int_ba+0x00 r irq0 (bod) i nterrupt s ource i dentity 0xxxxx_xxxx irq1_src int_ba+0x04 r irq1 (wd t ) i nterrupt s ource i dentity 0xxxxx_xxxx irq2_src int_ba+0x08 r irq2 (eint0) i nterrupt s ource i dentity 0xxxxx_xxxx irq3_src int_ba+0x0c r irq3 (eint1) i nterrupt s ource i dentity 0xxxxx_xxxx irq4_src int_ba+0x10 r irq4 (gpa/ gp b) i nterrupt s ource i dentity 0xxxxx_xxxx irq5_src int_ba+0x14 r irq5 (gpc/ gp d/ gp e / gp f ) i nterrupt s ource i dentity 0xxxxx_xxxx irq6_src int_ba+0x18 r irq6 (pwm a ) i nterrupt s ource i dentity 0xxxxx_xxxx irq7_src int_ba+0x1c r irq7 (pwm b ) i nterrupt s ource i dentity 0xxxxx_xxxx irq8_src int_ba+0x20 r irq8 (tmr0) i nterrupt s ource i dentity 0xxxxx_xxxx irq9_src int_ba+0x24 r irq9 (tmr1) i nterrupt s ource i dentity 0xxxxx_xxxx irq10_src int_ba+0x28 r irq10 (tmr2) i nterrupt s ource i dentity 0xxxxx_xxxx irq11_src int_ba+0x2c r irq11 (tmr3) i nterrupt s ource i dentity 0xxxxx_xxxx irq12_src int_ba+0x30 r irq12 (u a rt0 / uart 2 ) i nterrupt s ource i dentity 0xxxxx_xxxx irq13_src int_ba+0x34 r irq13 (u a rt1) i nterrupt s ource i dentity 0xxxxx_xxxx irq14_src int_ba+0x38 r irq14 (spi0) i nterrupt s ource i dentity 0xxxxx_xxxx irq15_src int_ba+0x3c r irq15 (spi1) i nterrupt s ource i dentity 0xxxxx_xxxx irq16_src int_ba+0x40 r irq16 (spi2) i nterrupt s ource i dentity 0xxxxx_xxxx irq17_src int_ba+0x44 r irq17 (spi3) i nterrupt s ource i dentity 0xxxxx_xxxx irq18_src int_ba+0x48 r irq18 (i 2 c0) i nterrupt s ource i dentity 0xxxxx_xxxx irq19_src int_ba+0x4c r irq19 (i 2 c1) i nterrupt s ource i dentity 0xxxxx_xxxx irq20_src int_ba+0x50 r reserved 0xxxxx_xxxx irq21_src int_ba+0x54 r reserved 0xxxxx_xxxx irq22_src int_ba+0x58 r irq22 ( sc 0/ sc 1 / sc 2 ) i nterrupt s ource i dentity 0xxxxx_xxxx
n u m icro ? j an 31 , 201 9 page 53 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet irq23_src int_ba+0x5c r irq23 (usb) i nterrupt s ource i dentity 0xxxxx_xxxx irq24_src int_ba+0x60 r irq24 (ps / 2) i nterrupt s ource i dentity 0xxxxx_xxxx irq25_src int_ba+0x64 r irq25 (acmp) i nterrupt s ource i dentity 0xxxxx_xxxx irq26_src int_ba+0x68 r irq26 (pdma) i nterrupt s ource i dentity 0xxxxx_xxxx irq27_src int_ba+0x6c r irq27 ( i 2 s ) i nterrupt s ource i dentity 0xxxxx_xxxx irq28_src int_ba+0x70 r irq28 (pwrwu) i nterrupt s ource i dentity 0xxxxx_xxxx irq29_src int_ba+0x74 r irq29 (adc) i nterrupt s ource i dentity 0xxxxx_xxxx irq30_src int_ba+0x78 r irq30 ( irc t ) i nterrupt s ource i dentity 0xxxxx_xxxx irq31_src int_ba+0x7c r irq31 (rtc) i nterrupt s ource i dentity 0xxxxx_xxxx nmi_sel int_ba+0x80 r/w nmi source interrupt select control register 0x0000_0000 mcu_irq int_ba+0x84 r/w mcu i nterrupt r equest s ource r egister 0x0000_0000
n u m icro ? j an 31 , 201 9 page 54 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.2.7 system control (scs) the cortex? - m0 status and operating mode control are managed by system control registers . including cpuid, cortex? - m0 interrupt priority and cortex? - m0 power management can be controlled through these system control register s for more detailed information, please refer to the arm ? cortex? - m0 technical reference manual and arm ? v6 - m architecture reference manual. 5.3 clock controller 5.3.1 overview the clock controller generates clock s for the whole chip , includ ing system clocks and all peripheral clocks . the clock controller also implements the power control function with the individually clock on/off control, clock source select ion and clock divider . the chip enters power - down mode when cortex? - m0 core execute s the wfi i nstruction only if the pwr_down_en (pwrcon[7]) bit and pd_wait_cpu (pwrcon[8]) bit are both set to 1 . a fter that, chip enter s p ower - down mode and wait s for wake - up interrupt source triggered to exit p ower - down mode. i n p ower - down mode, the clock controller turn s off the external 4~24 mhz high speed crystal and internal 22 .1184 mhz high speed oscillator to reduce the overall system power consumption.
n u m icro ? j an 31 , 201 9 page 55 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet figure 5 - 4 clock g enerator g lobal v iew d iagram 1 0 p l l c o n [ 1 9 ] 2 2 . 1 1 8 4 m h z 4 ~ 2 4 m h z p l l f o u t 1 1 1 0 1 1 0 1 0 0 0 1 4 ~ 2 4 m h z 3 2 . 7 6 8 k h z 4 ~ 2 4 m h z h c l k 2 2 . 1 1 8 4 m h z 0 0 0 1 / 2 1 / 2 1 / 2 c l k s e l 0 [ 5 : 3 ] 1 0 s y s t i c k t m r 0 a d c u a r t 0 - 2 p d m a a c m p i 2 c 0 ~ 1 i 2 s r t c p w m 0 - 1 w d t p w m 2 - 3 p w m 4 - 5 p w m 6 - 7 t m r 3 t m r 2 t m r 1 c p u f m c 3 2 . 7 6 8 k h z 1 0 k h z 0 1 1 0 1 0 0 0 1 0 0 0 h c l k 3 2 . 7 6 8 k h z 4 ~ 2 4 m h z 1 1 1 0 1 1 0 1 0 0 0 1 p l l f o u t 3 2 . 7 6 8 k h z 4 ~ 2 4 m h z 1 0 k h z 2 2 . 1 1 8 4 m h z 0 0 0 c l k s e l 0 [ 2 : 0 ] s y s t _ c s r [ 2 ] c p u c l k 1 / ( h c l k _ n + 1 ) p c l k c p u c l k h c l k 1 1 0 1 0 0 p l l f o u t 4 ~ 2 4 m h z h c l k c l k s e l 1 [ 3 : 2 ] e x t e r n a l t r i g g e r c l k s e l 1 [ 2 2 : 2 0 ] c l k s e l 1 [ 1 8 : 1 6 ] c l k s e l 1 [ 1 4 : 1 2 ] c l k s e l 1 [ 1 0 : 8 ] 1 1 1 0 0 1 0 0 h c l k p l l f o u t 4 ~ 2 4 m h z 2 2 . 1 1 8 4 m h z 0 1 1 0 1 0 0 0 1 0 0 0 h c l k 4 ~ 2 4 m h z 2 2 . 1 1 8 4 m h z 3 2 . 7 6 8 k h z 2 2 . 1 1 8 4 m h z 3 2 . 7 6 8 k h z w w d t 1 0 k h z 1 / ( a d c _ n + 1 ) c l k s e l 2 [ 1 : 0 ] 1 1 1 0 c l k s e l 1 [ 1 : 0 ] h c l k 1 / 2 0 4 8 1 / ( u a r t _ n + 1 ) 2 2 . 1 1 8 4 m h z 4 ~ 2 4 m h z 0 1 3 2 . 7 6 8 k h z 1 1 0 1 0 0 p l l f o u t 4 ~ 2 4 m h z 2 2 . 1 1 8 4 m h z c l k s e l 1 [ 2 5 : 2 4 ] 2 2 . 1 1 8 4 m h z 1 0 1 1 0 1 0 0 p l l f o u t 4 ~ 2 4 m h z h c l k c l k s e l 3 [ 5 : 4 ] 2 2 . 1 1 8 4 m h z 1 0 s c 2 1 / ( s c 2 _ n + 1 ) c l k s e l 3 [ 3 : 2 ] c l k s e l 3 [ 1 : 0 ] s c 1 1 / ( s c 1 _ n + 1 ) s c 0 1 / ( s c 0 _ n + 1 ) 1 0 k h z 2 2 . 1 1 8 4 m h z 1 0 1 1 1 1 1 0 s p i 0 - 3 s y s t _ c s r [ 2 ] c p u c l k u s b 1 / ( u s b _ n + 1 ) p l l f o u t 1 1 1 0 0 1 0 0 h c l k 4 ~ 2 4 m h z 2 2 . 1 1 8 4 m h z 3 2 . 7 6 8 k h z c l k s e l 2 [ 3 : 2 ] f d i v b o d 1 0 k h z 1 1 1 0 c l k s e l 2 [ 1 7 : 1 6 ] 1 0 k h z c l k s e l 2 [ 1 1 : 4 ] c l k s e l 1 [ 3 1 : 2 8 ] 1 0 k h z 1 1 1 p s 2 2 2 . 1 1 8 4 m h z
n u m icro ? j an 31 , 201 9 page 56 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet
n u m icro ? j an 31 , 201 9 page 57 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.3.2 clock generator the clock generator consists of 5 clock sources as list ed below: ? one external 32 .768 khz low speed crystal ? one external 4~24 mhz high speed crystal ? one programmable pll fout (pll source consists of external 4~24 m hz high speed crystal and internal 22 .1184 m hz high speed oscillator ) ? one internal 2 2 .1184 mhz high speed oscillator ? one internal 10 khz low speed oscillator figure 5 - 5 clock g enerator b lock d iagram x t 1 _ o u t e x t e r n a l 4 ~ 2 4 m h z c r y s t a l x t l 1 2 m _ e n ( p w r c o n [ 0 ] ) x t 1 _ i n i n t e r n a l 2 2 . 1 1 8 4 m h z o s c i l l a t o r o s c 2 2 m _ e n ( p w r c o n [ 2 ] ) 0 1 p l l p l l _ s r c ( p l l c o n [ 1 9 ] ) p l l f o u t x 3 2 _ o u t e x t e r n a l 3 2 . 7 6 8 k h z c r y s t a l 3 2 . 7 6 8 k h z x t l 3 2 k _ e n ( p w r c o n [ 1 ] ) x 3 2 _ i n i n t e r n a l 1 0 k h z o s c i l l a t o r o s c 1 0 k _ e n ( p w r c o n [ 3 ] ) 4 ~ 2 4 m h z 2 2 . 1 1 8 4 m h z 1 0 k h z
n u m icro ? j an 31 , 201 9 page 58 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.3.3 system clock and systick clock the system clock has 5 clock sou rces which were generated from clock generator block. the clock source switch depends on the register hclk_ s ( clksel0[2:0]). the block diagram is show n in figure 5 - 6 . figure 5 - 6 system clock block diagram the clock source of systick in cortex? - m0 core can use cpu clock or external clock (syst_csr[2]). if using external clock, the systick clock (stclk) has 5 clock sources. the clock source switch depends on the setting of the register stclk_s (clksel0[5:3] ) . the block diagram is show n in figure 5 - 7 . figure 5 - 7 systick c lock control block diagram 1 1 1 0 1 1 0 1 0 0 0 1 p l l f o u t 3 2 . 7 6 8 k h z 4 ~ 2 4 m h z 1 0 k h z h c l k _ s ( c l k s e l 0 [ 2 : 0 ] ) 2 2 . 1 1 8 4 m h z 0 0 0 1 / ( h c l k _ n + 1 ) h c l k _ n ( c l k d i v [ 3 : 0 ] ) c p u i n p o w e r d o w n m o d e c p u a h b a p b c p u c l k h c l k p c l k 1 1 1 0 1 1 0 1 0 0 0 1 4 ~ 2 4 m h z 3 2 . 7 6 8 k h z 4 ~ 2 4 m h z h c l k s t c l k _ s ( c l k s e l 0 [ 5 : 3 ] ) s t c l k 2 2 . 1 1 8 4 m h z 0 0 0 1 / 2 1 / 2 1 / 2
n u m icro ? j an 31 , 201 9 page 59 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.3.4 peripherals clock the peripherals clock can be selected as different clock source depends on the clock source select control registers ( clksel1 , clksel2 and clksel3) . 5.3.5 power - d own m ode clock when chip enters p ower - down mode, system clocks, some clock sources, and some peripheral clocks will be disabled. some clock sources and peripherals clock s are still active in p ower - down mode. the clocks still kep t active are list ed below: ? clock generator ? internal 10 khz low speed oscillator clock ? external 32 .768 khz low speed crystal clock ? peripherals clock ( w hen ip adopt external 32 .768 khz low speed crystal oscillator or 10 k hz low speed oscillator as clock source)
n u m icro ? j an 31 , 201 9 page 60 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.3.6 frequency divider output this device is equipped with a power - of - 2 frequency divider which is composed by16 ch ained divide - by - 2 shift registers. one of the 16 shift register outputs selected by a sixteen to one multiplexer is reflected to clko function pin. therefore there are 16 options of power - of - 2 divided clocks with the frequency from f in /2 1 to f in /2 16 where fin is input clock frequency to the clock divider. the output formula is f out = f in /2 (n+1) , where f in is the input clock frequency, f out is the clock divider output frequency and n is the 4 - bit value in fsel (frqdiv[3:0]). when writ ing 1 to divider_en (frqdiv[4]), the chained counter starts to count. when writ ing 0 to divider_en (frqdiv[4]), the chained counter continuously runs till divided clock reaches low state and stay in low state. i f divider1(frqdiv[5]) is set to 1, the frequency divider clock (frqdiv_clk) will bypass power - of - 2 frequency divider. the frequency divider clock will be output to c l ko pin directly. figure 5 - 8 clock source of fr e quency divider figure 5 - 9 frequency divider block diagram 1 1 1 0 0 1 0 0 h c l k 3 2 . 7 6 8 k h z 4 ~ 2 4 m h z 1 0 k h z f r q d i v _ s ( c l k s e l 2 [ 3 : 2 ] ) f d i v _ e n ( a p b c l k [ 6 ] ) f r q d i v _ c l k 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 : : 1 6 t o 1 m u x 1 / 2 1 / 2 2 1 / 2 3 1 / 2 1 5 1 / 2 1 6 . . . f s e l ( f r q d i v [ 3 : 0 ] ) c l k o f r q d i v _ c l k 1 6 c h a i n e d d i v i d e - b y - 2 c o u n t e r d i v i d e r _ e n ( f r q d i v [ 4 ] ) e n a b l e d i v i d e - b y - 2 c o u n t e r
n u m icro ? j an 31 , 201 9 page 61 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.4 usb device controller (usb) 5.4.1 overview there is one set of usb 2.0 full - speed device controller and transceiver in this device , which is compliant with usb 2.0 full - speed device specification and support s control/bulk/interrupt/ isochronous transfer types. in this device controller, there are two main interfaces: the apb bus and usb bus which comes from the usb phy transceiver. f or the apb bus, the cpu can program control registers through it. there are 512 bytes internal sram as data buffer in this controller. for in or out transfer, it is necessary to write data to sram or read data from sram through the apb interface or sie. us er needs to set the effective starting address of sram for each endpoint buffer through buffer segmentation register ( usb_ bufsegx). there are 6 endpoints in this controller. each of the endpoint can be configured as in or out endpoint. all the operations including control, bulk, interrupt and isochronous transfer are implemented in this block. the block of endpoint control is also used to manage the data sequential synchronization, endpoint states, current start address, transaction status, and data buffe r status for each endpoint. there are four different interrupt events in this controller. they are the wake - up function, device plug - in or plug - out event , usb events, e.g. in ack, out ack, and bus events, e.g. suspend and resume. any e vent will cause an in terrupt, and users just need to check the related event flags in interrupt event status register (usb_intsts) to acknowledge what kind of interrupt occurring, and then check the related usb endpoint status register (usb_epsts) to acknowledge what kind of e vent occurring in this endpoint . a software - disable function is also suppor ted for this usb controller. it is used to simulate the disconnection of this device from the host. if user enables drv se0 bit (usb_drvse0), the usb controller will force the output of usb_dp and usb_dm to level low and its function is disabled . after disable the drv se0 bit , host will enumerate the usb device again. please refer to universal serial bus specification revision 1.1 . 5.4.2 features this universal serial bus (usb) performs a s erial interface with a single connector type for attaching all usb peripherals to the host system. following is the feature list of this usb. ? compliant with usb 2.0 full - speed specification ? provide s 1 interrupt vector with 4 different interrupt events ( wak e - up , fldet, usb and bus) ? support s control/bulk/interrupt/isochronous transfer type ? support s suspend function when no bus activity existing for 3 ms ? provide s 6 endpoints for configurable control/bulk/interrupt/isochronous transfer types and maximum 512 byt es buffer size ? provide s remote wake - up capability
n u m icro ? j an 31 , 201 9 page 62 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.5 general purpose i/o (gpio) 5.5.1 overview the numicro ? nuc 2 0 0 series has u p to 8 0 general purpose i/o pins to be shared with other function pins depend ing on the chip configuration. these 8 0 pins are arranged in 6 ports named as gpioa, gpiob, gpioc, gpiod , gpioe and gpio f . the gpioa/b/c/d/e port has the maximum of 16 pins and gpiof port has the maximum of 4 pins . each o f the 8 0 pins is independent and has the corresponding register bits to control the pin mode function and data. the i/o type of each of i/o pins can be configured by software individually as input, output, open - drain or q uasi - bidirectional mode. after reset, the i/o mode of all pins are depending on config0[10] setting . in quasi - bidirectional mode, i/o pin has a very weak individual pull - up resistor which is about 110~300 k ? for v dd is from 5.0 v to 2.5 v. 5.5.2 features ? four i/o modes: ? quasi - bidirection al ? push - p ull output ? open - drain output ? input only with high impendence ? ttl/schm itt trigger input selectable by gpx_type[15:0] in gpx_mfp[ 31 : 16 ] ? i/o pin configured as interrupt source with edge/level setting ? configurable default i/o mode of all pins after reset by config0[10] setting ? if config [10] is 0, all gpio pins in input tri - state mode after chip reset ? if config [10] is 1, all gpio pins in q uasi - bidirectional mode after chip reset ? i/o pin internal pull - up resistor enabled only in q uasi - bidirectional i/o mode ? enabl ing the pin interrupt function will also enable the pin wake - up function .
n u m icro ? j an 31 , 201 9 page 63 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.6 i 2 c serial interface controller ( i 2 c ) 5.6.1 overview i 2 c is a two - wire, bidirectional serial bus that provides a simple and efficient method of data exchange between devices. the i 2 c standard is a true multi - master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. data is transferred between a master and a slave . data bits transfer on the scl and sda lines are synchronously on a byte - by - byte basi s. each data byte is 8 - bit long. there is one scl clock pulse for each data bit with the msb being transmitted first , and a n acknowledge bit follows each transferred byte. each bit is sampled during the high period of scl; therefore, the sda line may be ch anged only during the low period of scl and must be held stable during the high period of scl. a transition on the sda line while scl is high is interpreted as a command (start or stop). please refer to figure 5 - 10 for more detail ed i 2 c bus timing. figure 5 - 10 i 2 c bus timing the devices on - chip i 2 c logic provides a serial interface that meets the i 2 c bus standard mode specification. the i 2 c port handles byte transfers autonomously. to enable this port, the bit ens1 in i2con should be set to '1'. the i 2 c h/w interfaces to the i 2 c bus via two pins: sda and scl. pull - up resist or is needed for i 2 c operation as the sda and scl are open drain pins. when i/o pins are used as i 2 c port s , user must set the pins function to i 2 c in advance. t b u f s t o p s d a s c l s t a r t t h d ; s t a t l o w t h d ; d a t t h i g h t f t s u ; d a t r e p e a t e d s t a r t t s u ; s t a t s u ; s t o s t o p t r
n u m icro ? j an 31 , 201 9 page 64 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.6.2 features the i 2 c bus uses two wires (sda and scl) to transfer information between devices connected to the bus. the main features of the bus include : ? master/ slave mode ? bidirectional data transfer between masters and slaves ? multi - master bus (no central master) ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus ? serial clock synchronization allow ing devices with different bit rates to communicate via one serial bus ? serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer ? a b uilt - in 14 - bit time - out counter request ing the i 2 c interrupt if the i 2 c bus hangs up and timer - out counter overflows. ? external pull - up resistors needed for high output ? programmable clocks allow ing for versatile rate control ? supports 7 - bit addressing mode ? s upport s multiple address recognition ( f our slave address es with mask option)
n u m icro ? j an 31 , 201 9 page 65 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.7 pwm generator and capture timer (pwm) 5.7.1 overview the numicro ? nuc 200 series has 2 sets of pwm group support ing a total of 4 sets of pwm g enerators that can be configured as 8 independent pwm outputs, pwm0~pwm7, or as 4 complementary pwm pairs, (pwm0, pwm1), (pwm2, pwm3), (pwm4, pwm5) and (pwm6, pwm7) with 4 programmable d ead - zone generators. each pwm g enerator has one 8 - bit prescaler, one c lock divider with 5 divided frequencies (1, 1/2, 1/4, 1/8, 1/16), two pwm timers including two clock selectors, two 16 - bit pwm counters for pwm period control, two 16 - bit comparators for pwm duty control and one d ead - zone generator. the 4 sets of pwm g ener ators provide eight independent pwm interrupt flags set by hardware when the corresponding pwm period down counter reaches 0 . each pwm interrupt source with its corresponding enable bit can cause cpu to request pwm interrupt. the pwm generators can be conf igured as one - shot mode to produce only one pwm cycle signal or auto - reload mode to output pwm waveform continuously. when pcr.dzen01 is set, pwm0 and pwm1 perform complementary pwm paired function; the paired pwm period, duty and d ead - time are determined by pwm0 timer and dead - zone generator 0. similarly, the complementary pwm pairs of (pwm2, pwm3), (pwm4, pwm5) and (pwm6, pwm7) are controlled by pwm2, pwm4 and pwm6 timers and dead - zone generator 2, 4 and 6, respectively. refer to e` ! ??? and e` ! ??? for the architecture of pwm timers. to pr event pwm driving output pin with unsteady waveform, the 16 - bit period down counter and 16 - bit comparator are implemented with double buffer. when user writes data to counter/comparator buffer registers the updated value will be load into the 16 - bit down c ounter/ comparator at the time down counter reaching 0 . the double buffering feature avoids glitch at pwm outputs. when the 16 - bit period down counter reaches 0 , the interrupt request is generated. if pwm - timer is set as auto - reload mode, when the down cou nter reaches 0 , it is reloaded with pwm counter register (cnrx) automatically then start decreasing, repeatedly. if the pwm - timer is set as one - shot mode, the down counter will stop and generate one interrupt request when it reaches 0 . the value of pwm cou nter comparator is used for pulse high width modulation. the counter control logic changes the output to high level when down - counter value matches the value of compare register. the alternate feature of the pwm - timer is digital input capture function. if capture function is enabled the pwm output pin is switched as capture input mode. the capture0 and pwm0 share one timer which is included in pwm0 and the capture1 and pwm1 share pwm1 timer, and etc. therefore user must setup the pwm - timer before enable cap ture feature. after capture feature is enabled, the capture always latched pwm - counter to capture rising latch register (crlr) when input channel has a rising transition and latched pwm - counter to capture falling latch register (cflr) when input channel ha s a falling transition. capture channel 0 interrupt is programmable by setting ccr0. c rl_ie0[1] (rising latch interrupt enable) and ccr0. c fl_ie0[2]] (falling latch interrupt enable) to decide the condition of interrupt occur. capture channel 1 has the same feature by setting ccr0. c rl_ie1[17] and ccr0. c fl_ie1[18]. and capture channel 2 to channel 3 on each group have the same feature by setting the corresponding control bits in ccr2. for each group, whenever capture issues interrupt 0/1/2/3, the pwm counter 0 /1/2/3 will be reload at this moment. the maximum captured frequency that pwm can capture is confined by the capture interrupt latency. when capture interrupt occurred, software will do at least three steps, including: read piir to get interrupt source and read crl r x/cfl r x(x=0~3) to get capture value and finally write 1 to clear piir to 0 . if interrupt latency will take time t0 to finish, the capture signal mustnt transition during this interval (t0). in this case, the maximum capture frequency will be 1/t0. for example:
n u m icro ? j an 31 , 201 9 page 66 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet hclk = 50 mhz, pwm_clk = 25 mhz, interrupt latency is 900 ns so the maximum capture frequency will be 1/900ns 1000 khz 5.7.2 features 5.7.2.1 pwm function: ? up to 2 pwm group s (pwma/pwmb) to support 8 pwm channels or 4 complementary pwm paired channels ? each pwm group has two pwm generators with e ach pwm generator support ing one 8 - bit prescaler, two clock divider, two pwm - timers, one d ead - zone generator and two pwm outputs. ? up to 16 - bit resolution ? pwm interrupt request synchronized with pwm period ? one - shot or auto - reload mode pwm ? edge - aligned type or c enter - aligned type option 5.7.2.2 capture function: ? timing control logic shared with pwm g enerators ? support s 8 capture input channels shared with 8 pwm output channels ? eac h channel supports one rising latch register (crlr), one falling latch register (cflr) and capture interrupt flag (capifx)
n u m icro ? j an 31 , 201 9 page 67 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.8 real time clock (rtc) 5.8.1 overview the real time clock (rtc) controller provides user with the real time and calendar message. the clock source of rtc controller is from an external 32.768 khz low speed crystal which connected at pins x32 _ i n and x32 _ o ut (refer to pin d escription) or from an external 32.768 khz low speed oscillator output fed at pin x32 _ i n . the rtc controller provides the real time message ( hour , minute , second) in tlr (rtc time loading register ) as well as calendar message ( year , month , day) in clr (rtc calendar loading register ) . it also offers rtc alarm function that user can preset the alarm time in tar (rtc time al arm register ) and alarm calendar in car (rtc calendar alarm register ) . the data format of rtc time and calendar message are all expressed in bcd format. the rtc controller supports periodic rtc time tick and alarm match interrupts. the periodic rtc time ti ck interrupt has 8 period interval options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second which are selected by ttr (ttr[2:0] time tick register ). when real time and calendar message in tlr and clr are equal to alarm time and calendar setting s in tar and car, the aif (riir [0] rtc alarm interrupt flag ) is set to 1 and the rtc alarm interrupt signal is generated if the aier (rier [0] alarm interrupt enable ) is enabled. both rtc time tick and alarm match interrupt signal can cause chip to wake - up fr om idle or p ower - down mode if the correlate interrupt enable bit (aier or tier) is set to 1 before chip enter s idle or p ower - down mode . 5.8.2 features ? supports real time counter in tlr ( hour , minute , second) and calendar counter in clr ( year , month , day) for rtc time and calendar check ? supports alarm time (hour , minute , second ) and calendar (year , month , day) settings in tar and car ? selectable 12 - hour or 24 - hour time scale in tssr register ? supports leap y ear indication in lir register ? supports day of the w eek counter in dwr register ? frequency of rtc clock source compensate by fcr register ? all time and calendar message expressed in bcd format ? support s periodic rtc t ime t ick interrupt with 8 period interval options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second ? support s rtc time tick and alarm match interrupt ? support s chip wake - up from idle or p ower - down mode while a rtc interrupt signal is generated
n u m icro ? j an 31 , 201 9 page 68 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.9 serial peripheral interface (spi) 5.9.1 overview the serial peripheral interface ( spi ) is a synchronous serial data communication protocol that operates in full duplex mode. devices communicate in m aster/ slave mode with the 4 - wire bi - direction interface. the numicro ? nuc 2 00 series contains up to four sets of spi controller s perform ing a serial - to - parallel conversion on data received from a peripheral device , and a parallel - to - serial conversion on data transmitted to a peripheral device . each set of spi controller can be configured as a master or a slave device . th e spi controller suppo rts the variable serial clock function for special application s and 2 - bit t ransfer mode to connect 2 off - chip slave devices at the same time. this controller also supports the pdma function to access the data buffer and also support s d ual i / o t ransfer mode . 5.9.2 features ? up to four sets of spi controller s ? support s m aster or slave mode operation ? support s 2 - bit t ransfer mode ? support s d ual i/o t ransfer mode ? configurable bit length of a transfer word from 8 to 32 - bit ? provide s separate 8 - layer depth transmit and receive fifo buffers ? support s msb first or lsb first transfer sequence ? two slave select li nes in master mode ? support s the byte reorder function ? support s b yte or w ord s uspend mode ? variable output serial clock frequency in master mode ? support s pdma transfer ? support s 3 - wire, no slave select signal, bi - direction interface
n u m icro ? j an 31 , 201 9 page 69 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.10 timer controller (tmr) 5.10.1 overview the timer controller includes four 32 - bit timers, timer0~timer3, allow ing user to easily implement a timer control for applications. the timer can perform functions , such as frequency measurement, event counting, interval measurement, clock generation, and delay timing. the timer can generate an interrupt signal upon time - out, or provide the current value during operation. 5.10.2 features ? four sets of 32 - bit timers with 24 - bit up counter and one 8 - bit prescale counter ? independent clock source for each timer ? provides one - shot, periodic, toggle and continuous counting operation modes ? time - out period = (period of timer clock input) * (8 - bit prescale counte r + 1) * (24 - bit tcmp) ? maximum counting cycle time = (1 / t mhz) * (2 8 ) * (2 24 ), t is the period of timer clock ? 24 - bit up counter value is readable through tdr (timer data register) ? support s event counting function to count the event from external pin ? supp ort s external pin capture function for interval measurement ? support s external pin capture function for reset timer counter ? supports chip wake - up from idle/power - down mode if a timer interrupt signal is generated (tif set to 1)
n u m icro ? j an 31 , 201 9 page 70 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.11 watchdog timer (wdt) 5.11.1 overview the purpose of watchdog timer is to perform a system reset when system runs into an unknown state. this prevents system from hanging for an infinite period of time. besides, this watchdog timer supports the function to wake - up system from idle/ p ow er - down mode. 5.11.2 features ? 18 - bit free running up counter for watchdog t imer time - out interval . ? selectable time - out interval (2 4 ~ 2 18 ) and the time - out interval is 104 ms ~ 26.3168 s if wdt_clk = 10 khz. ? system ke pt in reset state for a period of (1 / wdt_clk) * 63 ? supports selectable watchdog t imer reset delay period, it includes (1024+2) (128+2) (16+2) or (1+2) wdt_clk reset delay period . ? supports force watchdog t imer enabled after chip powered on or reset while cwdten (config0[31] watchdog enable) bit is set to 0. ? supports watchdog t imer time - out wake - up function when wdt clock source is selected to 10 khz low speed oscillator. 5.12 window watchdog timer (wwdt) 5.12.1 overview the purpose of window watchdog timer is to perform a system reset within a specified window period to prevent software run to uncontrollable status by any unpredictable condition. 5.12.2 features ? 6 - bit down counter (wwdtval[5:0]) and 6 - bit compare value (wwdtcr[21:16] C wincmp value) to make the window p eriod flexible ? selectable maximum 11 - bit wwdt clock prescale (wwdtcr[11:8] C periodsel value) to make wwdt time - out interval variable
n u m icro ? j an 31 , 201 9 page 71 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.13 uart interface controller (uart) the numicro ? nuc 200 series provides up to three channels of universal asynchronous receiver/transmitters (uart). uart0 supports high speed uart and uart1~2 perform normal speed uart . b esides, only uart0 and uart1 support the flow control function. 5.13.1 overview the universal a synchronous receiver/transmitter (uart) performs a serial - to - parallel conversion on data received from the peripheral, and a parallel - to - serial conversion on data transmitted from the cpu. the uart controller also supports irda sir, lin master/ s lave mode a nd rs - 485 mode functions. each uart channel supports seven types of interrupts including : ? t ransmitter fifo empty interrupt (int_thre ) ; ? r eceiver threshold level reach ed interrupt (int_rda) ; ? l ine status interrupt (parity error or fram e error or break interrupt) (int_rls) ; ? r eceiver buffer time - out interrupt (int_tout) ; ? modem/wake - up status interrupt (int_modem) ; ? buffer error interrupt (int_buf_err) ; ? lin interrupt (int_lin) . interrupts of uart0 and uart2 share the interrupt number 12 (vector number is 28); interrupt number 13 (vector number is 29) only supports uart1 interrupt. refer to the nested vectored interrupt controller chapter f or system interrupt map. the uart0 is bui lt - in with a 64 - byte transmitter fifo (tx_fifo) and a 64 - byte receiver fifo (rx_fifo) that reduces the number of interrupts presented to the cpu . t he uart1~2 are equipped with 16 - byte transmitter fifo (tx_fifo) and 16 - byte receiver fifo (rx_fifo). the cpu can read the status of the uart at any time during the operation. the reported status information includes the type and condition of the transfer operations being performed by the uart, as well as 4 error conditions (parity error, fram e error, break interr upt and buffer error) probably occur while receiving data. the uart includes a programmable baud rate generator that is capable of dividing clock input by divisors to produce the serial clock that transmitter and receiver need. the baud rate equation is ba ud rate = uart_clk / m * [brd + 2], where m and brd are defined in baud rate divider register (ua_baud). table 5 - 5 l ist s the equations in the various conditions and table 5 - 6 list s the uart baud rate setting table. mode div_x_en div_x_one divider x brd baud r ate e quation 0 0 0 dont care a uart_clk / [16 * (a+2)] 1 1 0 b a uart_clk / [(b+1) * (a+2)] , b must >= 8 2 1 1 dont care a uart_clk / (a+2), a must >=3 table 5 - 5 uart baud rate equation system clock = internal 22.1184 mhz high speed oscillator baud r ate mode 0 mode 1 mode 2 parameter register parameter register parameter register 921600 x x a=0,b=11 0x2b00_0000 a=22 0x3000_0016
n u m icro ? j an 31 , 201 9 page 72 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 460800 a=1 0x0000_0001 a=1,b=15 a=2,b=11 0x2f00_0001 0x2b00_0002 a=46 0x3000_002e 230400 a=4 0x0000_0004 a=4,b=15 a=6,b=11 0x2f00_0004 0x2b00_0006 a=94 0x3000_005e 115200 a=10 0x0000_000a a=10,b=15 a=14,b=11 0x2f00_000a 0x2b00_000e a=190 0x3000_00be 57600 a=22 0x0000_0016 a=22,b=15 a=30,b=11 0x2f00_0016 0x2b00_001e a=382 0x3000_017e 38400 a=34 0x0000_0022 a=62,b=8 a=46,b=11 a=34,b=15 0x2800_003e 0x2b00_002e 0x2f00_0022 a=574 0x3000_023e 19200 a=70 0x0000_0046 a=126,b=8 a=94,b=11 a=70,b=15 0x2800_007e 0x2b00_005e 0x2f00_0046 a=1150 0x3000_047e 9600 a=142 0x0000_008e a=254,b=8 a=190,b=11 a=142,b=15 0x2800_00fe 0x2b00_00be 0x2f00_008e a=2302 0x3000_08fe 4800 a=286 0x0000_011e a=510,b=8 a=382,b=11 a=286,b=15 0x2800_01fe 0x2b00_017e 0x2f00_011e a=4606 0x3000_11fe table 5 - 6 uart baud rate setting table the uart0 and uart1 controllers support the auto - flow control f unction that uses two low - level signals, n cts (clear - to - send) and n rts (request - to - send), to control the flow of data transfer between the chip and external devices ( e.g. modem). when auto - flow is enabled, the uart is not allowed to receive data until the uart asserts n rts to external device. when the number of bytes in the rx fifo equals the value of rts_tri_lev (ua_fcr [19:16]), the n rts is de - asserted. the uart sends dat a out when uart controller detects n cts is asserted from external device. if a valid asserted n cts is not detected the uart controller will not send data out. the uart controllers also provides serial irda (sir, serial infrared) function (user must set ird a_en (ua_fun_sel [1]) to enable irda function). the sir specification defines a short - range infrared asynchronous serial transmission mode with 1 start bit, 8 data bits, and 1 stop bit. the maximum data rate supports up to 115.2 kbps (half duplex). the ird a sir block contains an irda sir protocol encoder/decoder. the irda sir p rotocol encoder/decoder is half - duplex only. so it cannot transmit and receive data at the same time. the irda sir physical layer specifies a minimum 10ms transfer delay between trans mission and reception , and t his delay feature must be implemented by software. the alternate function of uart controllers is lin (local interconnect network) function. the lin mode is selected by setting the ua_fun_sel[1:0] to 01 . in lin mode, 1 start bi t and 8 data bits format with 1 stop bit are required in accordance with the lin standard. for numicro ? nuc200 series, another alternate function of uart controllers is rs - 485 9 - bit mode, and direction control provided by n rts pin or can program gpio (pb.2 for uart0_n rts and pb.6 for uart1_n rts) to implement the function by software. the rs - 485 mode is selected by setting the ua_fun_sel register to select rs - 485 function. the rs - 485 transceiver control is implemented using t he n rts control signal from an asynchronous serial port to enable the rs - 485 transceiver . in rs - 485 mode, many characteristics of the receiving and transmitting are same as uart.
n u m icro ? j an 31 , 201 9 page 73 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.13.2 features ? full duplex, asynchronous communications ? separate s receive / transmit 64/16/16 bytes (uart0/uart1/uart2) entry fifo for data payloads ? support s hardware auto flow control/flow control function ( n cts, n rts) and programmable n rts flow control trigger level (uart0 and uart1 support) ? programmable receiver buff er trigger level ? support s programmable baud - rate generator for each channel individually ? support s n cts wake - up function (uart0 and uart1 support) ? support s 7 - bit receiver buffer time - out detection function ? uart0/uart1 can through dma channels to receive/tra nsmit data ? programmable transmitting data delay time between the last stop and the next start bit by setting ua_tor [dly] register ? support s break error, frame error, parity error and receive / transmit buffer overflow detect function ? fully programmable serial - interface characteristics ? programmable data bit length , 5 - , 6 - , 7 - , 8 - bit character ? programmable parity bit, even, odd, no parity or stick parity bit generation and detection ? programmable stop bit length , 1, 1.5, or 2 stop bit generation ? irda sir fu nction mode ? support s 3 - /16 - bit duration for normal mode ? lin function mode ? support s lin master/ s lave mode ? support s programmable break generation function for transmitter ? support s break detect function for receiver ? rs - 485 function mode. ? support s rs - 485 9 - bi t mode ? support s hardware or software direct enable control provided by n rts pin
n u m icro ? j an 31 , 201 9 page 74 of 1 00 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.14 ps / 2 device controller (ps2d) 5.14.1 overview ps/2 device controller provides a basic timing control for ps/2 communication. all communication between the device and the host is managed through the ps2_ clk and ps2_ dat pins. unlike ps/2 keyboard or mouse device controller, the receive/transmit code need s to be translated as meaningful code by firmware. the device controller generates the ps2_ clk signal after receiving a r equest to s end state , but host has ultimate control over communication. data of ps2_ dat line sent from the host to the device is read on the rising edge and sent from the device to the host is change after rising edge. a 16 bytes fifo is used to reduce cpu intervention. s oftware can select 1 to 16 bytes for a continuous transmission. 5.14.2 features ? host communication inhibit and r equest to s end state detection ? reception fra me error detection ? programmable 1 to 16 bytes transmit buffer to reduce cpu intervention ? double buffer for data reception ? s o ftware overrid e bus
n u m icro ? j an 31 , 201 9 page 75 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.15 i 2 s controller (i 2 s) 5.15.1 overview the i 2 s controller consists of i 2 s protocol to interface with external audio codec. two 8 - word deep fifo for read path and write path respectively and is capable of handling 8 - , 16 - , 24 - and 32 - bit word sizes. p dma controller handle s the data movement between fifo and memory. 5.15.2 features ? o perate d as either m aster or s lave ? capable of handling 8 - , 16 - , 24 - and 32 - bit word sizes ? supports mono a nd stereo audio data ? supports i 2 s and msb justified data format ? provides t wo 8 - word fifo data buffers, one fo r transmit ting and the other for receiv ing ? generates interrupt requests when buffer levels cross a program mable boundary ? two p dma requests, one f or transmit ting and the other for receiv ing
n u m icro ? j an 31 , 201 9 page 76 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.16 analog - to - digital converter (adc) 5.16.1 overview the numicro ? nuc 200 series contains one 12 - bit successive approximation analog - to - digital converters (sar a/d converter) with 8 input channels. the a/d converter supports three operation modes: single, single - cycle scan and continuous scan mode. the a/d converter can be started by s oftware, pwm c enter - aligned trigger and external stadc pin. 5.16.2 features ? analog input voltage range: 0~v ref ? 12 - bit resolution and 10 - bit accuracy is guaranteed ? up to 8 single - end analog input channels or 4 differential analog input channels ? up to 76 0 k sps conv ersion rate as adc clock frequency is 16 mhz (chip working at 5v) ? three operating modes ? single mode: a/d conversion is performed one time on a specified channel ? single - cycle scan mode: a/d conversion is performed one cycle on all specified channels with th e sequence from the smallest numbered channel to the largest numbered channel ? continuous scan mode: a/d converter continuously performs single - cycle scan mode until software stops a/d conversion ? an a/d conversion can be started by : ? w rit ing 1 to adst bit through software ? pwm c enter - aligned trigger ? external pin stadc ? conversion results are held in data registers for each channel with valid and overrun indicators ? conversion result can be compared with specify value and user can select whether to generate an interrupt when conversion result matches the compare register setting ? channel 7 supports 3 input sources: external analog voltage, internal b and - gap voltage, and internal temperature sensor output
n u m icro ? j an 31 , 201 9 page 77 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.17 analog comparator ( a cmp) 5.17.1 overview the numicro ? nuc 200 series contains two comparators which can be used in a number of different configurations. the comparator output is logic 1 when positive input voltage is greater than negative input voltage ; otherwise the output is logic 0 . each comparator can be configur ed to cause an interrupt when the comparator output value changes. the block diagram is shown in e ` ! ??? . 5.17.2 features ? analog input voltage range: 0~ v dda ? supports hysteresis function ? supports optional internal reference voltage input at negative end for each comparator
n u m icro ? j an 31 , 201 9 page 78 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.18 p dma controller ( p dma) 5.18.1 overview the numicro ? nuc 200 series dma contains nine - channel peripheral direct memory access (pdma) controller and a cyclic redundancy check (crc) generator. the pdma that transfers data to and from memory or transfer data to and from apb devices. for pdma channel (pdma ch0~ch8), there is one - word buffer as transfer buffer between the peripherals apb devices and memory. software can stop the pdma operation by disable pdma pdma_csrx [pdmacen]. the cpu can recognize the completion of a pdma operation by software polling or when it receives an internal pdma interrupt. th e pdma controller can increase source or destination address or fixed them as well. the dma controller contains a cyclic redundancy check (crc) generator that can perform crc calculation with programmable polynomial settings. the crc engine support s cpu pi o mode and dma transfer mode. 5.18.2 features ? support s n ine p dma channels and one crc channel . each pdma channel can support a unidirectional transfer ? amba ahb master/slave interface compatible, for data transfer and register read/write ? hardware round robin priority scheme . dma channel 0 has the highest priority and channel 8 has the lowest priority ? pdma operation peripheral - to - memory, memory - to - peripheral, and memory - to - memory transfer support s word/half - word/byte transfer data width from/to peripheral suppo rt s address direction: increment, fixed. ? cyclic redundancy check (crc) supports four common polynomials crc - ccitt, crc - 8, crc - 16, and crc - 32 - crc - ccitt: x 16 + x 12 + x 5 + 1 - crc - 8: x 8 + x 2 + x + 1 - crc - 16: x 16 + x 15 + x 2 + 1 - crc - 32: x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 supports p rogrammable crc seed value. support s programmable order reverse setting for input data and crc checksum. support s programmable 1s complement setting for input data and crc checksum. support s cpu pio mode or dma transfer mode. support s the follows write data length in cpu pio mode - 8 - bit write mode (byte) : 1 - ahb clock cycle operation. - 1 6 - bit write mode (half - word) : 2 - ahb clock cycle operation. - 32 - bit write mode (word) : 4 - ahb clock cycle operation. support s byte alignment transfer data length and word alignment transfer source address in crc dma mode.
n u m icro ? j an 31 , 201 9 page 79 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.19 smart card host interface (sc) 5.19.1 overview the smart card interface controller (sc controller) is based on iso/iec 7816 - 3 standar d and fully compliant with pc/sc specifications. it also provides status of card insertion/removal. 5.19.2 features ? iso7816 - 3 t=0, t=1 compliant ? emv2000 compliant ? support s up to t hree iso7816 - 3 ports ? separate s receive / transmit 4 byte entry buffer for data payloads ? programmable transmission clock frequency ? programmable receiver buffer trigger level ? programmable guard time selection (11 etu ~ 266 etu) ? one 24 - bit and two 8 - bit time - out counter s for answer to request (atr) and waiting times processing ? support s auto inverse convention function ? support s transmitter and receiver error retry and error retry number limitation function ? support s hardware activation sequence process ? support s hardware war m reset sequence process ? support s hardware deactivation sequence process ? support s hardware auto deactivation sequence when detect ing the card removal
n u m icro ? j an 31 , 201 9 page 80 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 5.20 flash memory controller (fmc) 5.20.1 overview the numicro ? nuc 2 00 series has 128/64/32 k bytes on - chip embedded flash for application program memory (aprom) that can be updated through isp procedure. the in - system - programming (isp) function enables user to update program memory when chip is soldered on pcb. after chip is power ed on , cortex? - m0 cpu fetches code from aprom or ldrom decided by boot select (cbs) in config0. by the way, the numicro ? nuc 2 00 series also provide s additional data flash for user to store some application dependent data . for 128k bytes aprom device, the data flash is shared with original 128 k p rogram memory and its start address is configurable in config1. for 64k/32k bytes aprom device, the data flash is fixed at 4k . 5.20.2 features ? run s up to 5 0 mhz with zero wait state for continuous address read access ? all embedded flash memory supports 512 bytes page erase ? 128/64/32 k b application program memory (aprom) ? 4 k b i n - s ystem - p rogramming (isp) loader program memory (ldrom) ? 4kb data flash for 64/32 kb aprom device ? configurable data flash size for 128kb aprom device ? configurable or fixed 4 k b data flash with 512 bytes page erase unit ? support s in - application - programming (iap) to switch code between aprom and ldrom without reset ? in - system - program ming (isp) to update on - chip flash
n u m icro ? j an 31 , 201 9 page 81 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 6 application circuit a v s s a v d d a v c c d v c c v s s v d d 0 . 1 u f f b f b p o w e r c r y s t a l n u c 2 0 0 / 2 2 0 s e r i e s c d e v i c e l d o r s 2 3 2 t r a n s c e i v e r r o u t t i n r i n t o u t p c c o m p o r t 0 . 1 u f u a r t r x d t x d d v c c 1 0 u f / 1 0 v 1 0 k n r s t 4 ~ 2 4 m h z c r y s t a l 2 0 p 2 0 p x t 1 _ o u t x t 1 _ i n v d d v s s i 2 c l k d i o i 2 c _ s d a i 2 c _ s c l 4 . 7 k d v c c 4 . 7 k d v c c v b a t v r e f 3 2 . 7 6 8 k h z c r y s t a l 2 0 p 2 0 p x 3 2 _ o u t x 3 2 _ i n l d o _ c a p 1 u f r e s e t c i r c u i t v d d v s s s p i d e v i c e c s c l k m i s o s p i _ s s m o s i s p i _ c l k s p i _ m i s o s p i _ m o s i d v c c u s b o t g s l o t u s b _ v d d 3 3 _ c a p 1 u f u s b _ d - u s b _ d + u s b _ v b u s 1 u f 3 3 r 3 3 r v d d v s s n r e s e t i c e _ d a t i c e _ c l k s w d i n t e r f a c e 1 0 0 k d v c c 1 0 0 k [ 1 ] d v c c s m a r t c a r d s l o t s c _ p w r s c _ r s t s c _ c l k s c _ d a t s c _ d e t e c t n o t e 1 : i t i s r e c o m m e n d e d t o u s e p u l l - u p r e s i s t o r o n b o t h i c e _ d a t a n d i c e _ c l k p i n i f c i o i n i ( c o n f i g 0 [ 1 0 ] ) i s s e t t o 0 .
n u m icro ? j an 31 , 201 9 page 82 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 7 electrical characteristics 7.1 absolute maximum ratings symbol parameter min. max unit dc power supply v dd ? v ss - 0.3 +7.0 v input voltage v in v ss - 0.3 v dd +0.3 v oscillator frequency 1/t clcl 4 24 mhz operating temperature ta - 40 +85 ? c storage temperature tst - 55 +150 ? c maximum current into v dd - 120 ma maximum current out of v ss 120 ma maximum current sunk by a i/o pin 35 ma maximum current sourced by a i/o pin 35 ma maximum current sunk by total i/o pins 100 ma maximum current sourced by total i/o pins 100 ma note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability of the device.
n u m icro ? j an 31 , 201 9 page 83 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 7.2 dc electrical characteristics (v dd - v ss = 5.5 v, t a = 25 ? c, f osc = 50 mhz unless otherwise specified.) parameter sym. specification test conditions min. typ. max. unit operation v oltage v dd 2.5 5.5 v v dd = 2.5v ~ 5.5v up to 50 mhz power ground v ss av ss - 0.3 v ldo output voltage v ldo 1.62 1.8 1.98 v v dd > 2. 5 v analog operating voltage av dd v dd v when system used analog function, please refer to chapter 7.4 for corresponding analog operating voltage operating current normal run mode at 50 mhz i dd1 34 ma v dd = 5.5v , all ip and pll e nable d, xtal = 12 mhz i dd2 15 ma v dd = 5.5v, all ip d isable d and pll enabled , xtal = 12 mhz i dd3 32 ma v dd = 3 .3 v , all ip and pll enabled , xtal = 12 mhz i dd4 14 ma v dd = 3 .3 v , all ip disabled and pll enabled , xtal = 12 mhz operating current normal run mode at 12 mhz i dd5 8.5 ma v dd = 5.5v , all ip enabled and pll disabled , xtal = 12 mhz i dd6 3.6 ma v dd = 5.5v, all ip and pll disabled , xtal = 12 mhz i dd7 7.5 ma v dd = 3 .3 v, all ip enabled and pll disabled , xtal = 12 mhz i dd8 2.6 ma v dd = 3 .3 v, all ip and pll disabled , xtal = 12 mhz
n u m icro ? j an 31 , 201 9 page 84 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet parameter sym. specification test conditions min. typ. max. unit operating current normal run mode at 4 mhz i dd9 3.6 ma v dd = 5 .5 v, all ip enabled and pll disabled , xtal = 4 mhz i dd10 2 ma v dd = 5 .5 v, all ip and pll disabled , xtal = 4 mhz i dd11 2.8 ma v dd = 3 .3 v , all ip enabled and pll disabled , xtal = 4 mhz i dd12 1.2 ma v dd = 3 .3 v , all ip and pll disabled , xtal = 4 mhz operating current normal run mode at 32.768 khz i dd13 141 ? a v dd = 5 .5 v, all ip enabled and pll disabled , x tal = 32.768 khz i dd14 129 ? a v dd = 5 .5 v, all ip and pll disabled , x tal = 32.768 khz i dd15 138 ? a v dd = 3 .3 v , all ip enabled and pll disabled , x tal = 32.768 khz i dd16 125 ? a v dd = 3 .3 v , all ip and pll disabled , x tal = 32.768 khz operating current normal run mode at 10 khz i dd17 125 ? a v dd = 5 .5 v, all ip enabled and pll disabled , lirc10 khz enabled i dd18 120 ? a v dd = 5 .5 v, all ip and pll disabled , lirc10 khz enabled i dd19 125 ? a v dd = 3 .3 v , all ip enabled and pll disabled , lirc10 khz enabled
n u m icro ? j an 31 , 201 9 page 85 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet parameter sym. specification test conditions min. typ. max. unit i dd20 120 ? a v dd = 3 .3 v , all ip and pll disabled , lirc10khz enabled operating current idle mode at 50 mhz i idle1 28 ma v dd = 5.5v, all ip and pll e nable d, xtal = 12 mhz i idle2 10 ma v dd = 5.5v , all ip disabled and pll enabled, xtal = 12 mhz i idle3 27 ma v dd = 3 .3 v, all ip and pll enabled, xtal = 12 mhz i idle4 9 ma v dd = 3 .3v all ip disabled and pll enabled, xtal = 12 mhz operating current idle mode at 12 mhz i idle5 7.5 ma v dd = 5.5v, all ip enabled and pll disabled , xtal = 12 mhz i idle6 2.4 ma v dd = 5.5v, all ip and pll disabled , xtal = 12 mhz i idle7 6.5 ma v dd = 3 .3 v, all ip enabled and pll enabled , xtal = 12 mhz i idle8 1.5 ma v dd = 3 .3 v , all ip and pll disabled , xtal = 12 mhz operating current idle mode at 4 mhz i idle9 3.3 ma v dd = 5 .5v, all ip enabled and pll disabled, xtal = 4 mhz i idle10 1.7 ma v dd = 5 .5 v all ip and pll disabled, xtal = 4 mhz i idle11 2.4 ma v dd = 3 .3 v , all ip enabled and pll disabled, xtal = 4 mhz
n u m icro ? j an 31 , 201 9 page 86 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet parameter sym. specification test conditions min. typ. max. unit i idle12 0.8 ma v dd = 3 .3 v, all ip and pll disabled, xtal = 4 mhz operating current idle mode at 32.768 k hz i idle 13 133 ? a v dd = 5 .5 v, all ip enabled and pll disabled , x tal = 32.768 khz i idle1 4 120 ? a v dd = 5 .5 v, all ip and pll disabled , x tal = 32.768 khz i idle1 5 133 ? a v dd = 3 .3 v , all ip enabled and pll disabled , x tal = 32.768 khz i idle1 6 120 ? a v dd = 3 .3 v , all ip and pll disabled , x tal = 32.768 khz operating current idle mode at 10 k hz i idle 13 122 ? a v dd = 5 .5 v, all ip enabled and pll disabled , lirc10 khz enabled i idle1 4 118 ? a v dd = 5 .5 v, all ip and pll disabled , lirc10 khz enabled i idle1 5 122 ? a v dd = 3 .3 v , all ip enabled and pll disabled , lirc10 khz enabled i idle1 6 118 ? a v dd = 3 .3 v all ip and pll disabled , lirc10 khz enabled standby current power - down mode (deep sleep mode) i pwd1 15 ? a v dd = 5.5v, rtc disabled , when bo d function disabled i pwd 2 15 ? a v dd = 3. 3 v, rtc disabled , when bo d function disabled i pwd 3 17 ? a v dd = 5. 5 v, rtc enabled , when bo d function disabled i pwd 4 17 ? a v dd = 3. 3 v, rtc enabled , when bo d function disabled input current pa, pb, pc, pd, pe , pf (quasi - bidirectional mode) i in1 - 50 - 60 ? a v dd = 5.5v, v in = 0v or v in =v dd
n u m icro ? j an 31 , 201 9 page 87 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet parameter sym. specification test conditions min. typ. max. unit input current at n reset [1] i in2 - 55 - 45 - 30 ? a v dd = 3.3v, v in = 0.45v input leakage current pa, pb, pc, pd, pe , pf i lk - 2 - + 2 ? a v dd = 5.5v, 0 n u m icro ? j an 31 , 201 9 page 88 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet parameter sym. specification test conditions min. typ. max. unit sink current pa, pb, pc, pd, pe , pf (quasi - bidirectional and push - pull mode) i sk1 10 16 20 ma v dd = 4.5v, v s = 0.45v i sk1 7 10 13 ma v dd = 2.7v, v s = 0.45v i sk1 6 9 12 ma v dd = 2.5v, v s = 0.45v brown - out v oltage with bo d _vl [1:0] = 00b v bo2. 2 2. 1 2. 2 2. 3 v brown - out v oltage with bo d _vl [1:0] = 01b v bo2. 7 2.6 2.7 2.8 v brown - out voltage with bo d _vl [1:0] = 10b v bo3.8 3. 5 3. 7 3. 9 v brown - out v oltage with bo d _vl [1:0] = 11b v bo4.5 4. 2 4. 4 4. 6 v hysteresis range of bod voltage v b h 30 - 1 5 0 mv v dd = 2.5v~5.5v note: 1. n res e t pin is a schmitt trigger input. 2. crystal input is a cmos input. 7.3 3. pins of p a , p b , p c , p d , pe and p f can source a transition current when they are being ex ternally driven from 1 to 0. in the condition of v dd = 5.5 v, t he transition current reaches its maximum value when v in approximates to 2 v. ac electrical characteristics 7.3.1 external 4~24 mhz high speed oscillator note: duty cycle is 50%. symbol parameter condition min. typ . max. unit t chcx clock high time 1 0 - - ns t clcx clock low time 1 0 - - ns t clch clock rise time 2 - 1 5 ns t chcl clock fall time 2 - 1 5 ns 7.3.2 external 4~24 mhz high speed crystal parameter condition min. typ. . max. unit t c h c x 9 0 % 1 0 % t c l c h t c h c l t c l c x t c l c l 0 . 3 v d d 0 . 7 v d d
n u m icro ? j an 31 , 201 9 page 89 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet operation voltage v dd - 2. 5 - 5.5 v temperature - - 40 - 85 operating c urrent 12 mhz at v dd = 5v - 1 - ma c lock f requency external crystal 4 24 mhz 7.3.2.1 typical crystal application circuits crystal c1 c2 r 4 mhz ~ 24 mhz 10~20pf 10~20pf without figure 7 - 1 typical crystal application circuit 7.3.3 external 32 .768 khz low speed crystal oscillator parameter condition min. typ. max. unit operation voltage v dd - 2. 5 - 5.5 v operation temperature - - 40 - 85 operation current 32.768khz at v dd =5v 1.5 ? a c lock f requency external crystal - 32 .768 - khz 7.3.4 internal 22.1184 mhz high speed oscillator parameter condition min. typ. max. unit operation voltage v dd - 2.5 - 5.5 v center frequency - - 22.1184 - mhz calibrated internal oscillator frequency +25 ; v dd =5 v - 1 - +1 % x t 1 _ i n x t 1 _ o u t c 1 r c 2
n u m icro ? j an 31 , 201 9 page 90 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet - 40 ~+85 ; v dd =2.5 v~5.5 v - 3 - +3 % operation current v dd =5 v - 500 - ua 7.3.5 internal 10 khz low speed oscillator parameter condition min. typ. max. unit operation voltage v dd - 2.5 - 5.5 v center frequency - - 10 - khz calibrated internal oscillator frequency +25 ; v dd =5 v - 30 - +30 % - 40 ~+85 ; v dd =2.5 v~5.5 v - 50 - +50 % 7.4 analog characteristics 7.4.1 12 - bit saradc specification symbol parameter min. typ. max. unit - resolution - - 12 bit dnl differential nonlinearity error - - 1~2 - 1~4 lsb inl integral nonlinearity error - 2 4 lsb eo offset error - 1 10 lsb eg gain error (transfer gain) - 1 1.005 - - monotonic guaranteed f adc adc clock frequency ( a v dd = 5v/3v) - - 16 /8 mhz f s sample rate - - 7 60 k sps v dd a supply voltage 3 - 5.5 v i dd supply current (avg.) - 0.5 - ma i dda - 1.5 - ma v ref reference voltage 3 - v dd a v i ref reference current (avg.) - 1 - ma v in input voltage 0 - v ref v 7.4.2 ldo and power m anagement specification parameter min . typ . max . unit note
n u m icro ? j an 31 , 201 9 page 91 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet input voltage v dd 2. 5 5.5 v v dd input voltage output voltage 1.62 1.8 1.98 v v dd > 2. 5 v operating temperature - 40 25 85 cbp - 1 - ? f r esr = 1 ? note: 1. it is recommended that a 10 uf or higher capacitor and a 100 nf bypass capacitor are connected between v dd and the closest v ss pin of the device. 2. to ensur e power stability, a 1 ? f or higher capacitor must be connected between ldo _cap pin and the closest v ss pin of the device.
n u m icro ? j an 31 , 201 9 page 92 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 7.4.3 low voltage reset specification parameter condition min. typ. max. unit operation v oltage - 0 - 5.5 v quiescent c urrent v dd =5.5 v - 1 5 ? a operation t emperature - - 40 25 85 threshold v oltage temperature=25 1.7 2.0 2.3 v temperature= - 40 - 2.4 - v temperature=85 - 1.6 - v hysteresis - 0 0 0 v 7.4.4 brown - out detector specification parameter condition min. typ. max. unit operation v oltage - 0 - 5.5 v operation temperature - - 40 25 85 quiescent c urrent av dd =5.5 v - - 125 a brown - out v oltage bo d _vl [1:0]=11 4. 2 4. 4 4.6 v bo d _vl [1:0]=10 3. 5 3. 7 3.9 v bo d _vl [1:0]=01 2.6 2.7 2.8 v bo d _vl [1:0]=00 2. 1 2. 2 2. 3 v hysteresis - 30 - 150 mv 7.4.5 power - o n reset specification parameter condition min. typ. max. unit operation temperature - - 40 25 85 reset v oltage v+ - 2 - v quiescent c urrent vin > reset voltage - 1 - na
n u m icro ? j an 31 , 201 9 page 93 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 7.4.6 temperature sensor specification parameter condition min . typ . max . unit operation v oltage [1] 2.5 - 5.5 v operation t emperature - 40 - 8 5 current c onsumption 6.4 - 10.5 a gain - 1.76 mv/ offset v oltage temp=0 720 mv note: internal operation voltage comes from internal ldo. 7.4.7 comparator specification parameter condition min. typ. max. unit operation voltage a v dd - 2. 5 5.5 v operation temperature - - 40 25 85 operation c urrent v dd =3 .0 v - 20 40 a input o ffset v oltage - - 5 15 mv output s wing - 0.1 - v dd a - 0.1 v input c ommon m ode r ange - 0.1 - v dd a - 1.2 v dc g ain - - 70 - db propagation d elay vcm = 1.2 v and vdiff = 0.1 v - 200 - ns comparison v oltage 20 mv at vcm=1 v 50 mv at vcm=0.1 v 50 mv at vcm=v dd - 1.2 10 mv for non - hysteresis 10 20 - mv hysteresis vcm=0.4 v ~ v dd - 1.2 v - 10 - mv wake - up t ime cinp = 1.3 v cinn = 1.2 v - - 2 s
n u m icro ? j an 31 , 201 9 page 94 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 7.4.8 usb phy specification 7.4.8.1 usb dc electrical characteristics symbol parameter condition min. typ . max. unit v ih input h igh (driven) 2.0 v v il input l ow 0.8 v v di differential i nput s ensitivity |padp - padm| 0.2 v v cm differential c ommon - mode r ange includes v di range 0.8 2.5 v v se single - ended r eceiver t hreshold 0.8 2.0 v receiver h ysteresis 200 mv v ol output l ow (driven) 0 0.3 v v oh output h igh (driven) 2.8 3.6 v v crs output s ignal c ross v oltage 1.3 2.0 v r pu pull - up r esistor 1.425 1.575 k v trm termination voltage for u pstream p ort p ull - up (rpu) 3.0 3.6 v z drv driver o utput r esistance steady state drive* 10 c in transceiver c apacitance pin to gnd 20 pf *driver output resistance doesnt include series resistor resistance. 7.4.8.2 usb full - speed driver electrical characteristics symbol parameter condition min. typ . max. unit t fr rise time c l =50p 4 20 ns t ff fall time c l =50p 4 20 ns t frff rise and f all t ime m atching t frff =t fr /t ff 90 111.11 % 7.4.8.3 usb power dissipation symbol parameter condition min. typ . max. unit i v bus usb_ v bus current (steady state) standby 50 a
n u m icro ? j an 31 , 201 9 page 95 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 7.4.8.4 usb ldo specification symbol parameter condition min. typ. max. unit usb_ v bus usb_ vbus pin input voltage 4.0 5.0 5.5 v usb_ v dd33 _cap ldo output voltage 3.0 3.3 3.6 v c bp external bypass capacitor 1.0 - uf
n u m icro ? j an 31 , 201 9 page 96 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 7.5 flash dc electrical characteristics symbol parameter condition min. typ. max. unit v dd supply v oltage 1.62 1.8 1.98 v [2] t ret data retention at 85 10 year t erase page e rase t ime 2 ms t mer mass e rase t ime 10 ms t prog program t ime 20 s i dd 1 read c urrent - 0.15 0.5 m a /mh z i dd 2 program/erase c urrent 7 ma i pd power d own c urrent - 1 20 a 1. v dd is source from chip ldo output voltage. 2. this table is g uaranteed by design, not test in production.
n u m icro ? j an 31 , 201 9 page 97 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 8 package dimens i ons 8.1 100 - pin lqfp (14x14x1. 4 mm footprint 2.0 mm) controlling dimension : millimeters 0.10 0 7 0 0.004 1.00 0.75 0.60 0.45 0.039 0.030 0.024 0.018 0.638 0.630 0.622 0.50 14.10 0.20 0.27 1.45 1.60 14.00 1.40 13.90 0.10 0.17 1.35 0.05 0.008 0.011 0.057 0.063 0.055 0.020 0.556 0.551 0.547 0.004 0.007 0.053 0.002 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y a1 a 2 l1 e 0.009 0.006 0.15 0.22 7 13.90 14.00 14.10 15.80 16.00 16.20 15.80 16.00 16.20 0.556 0.551 0.547 ? 0.638 0.630 0.622 d d e e b a2 a1 a l1 e c l y h h 1 100 ? 25 26 50 51 7 5 7 6
n u m icro ? j an 31 , 201 9 page 98 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 8.2 64 - pin lqfp ( 7 x 7 x1 . 4 mm footprint 2.0 mm)
n u m icro ? j an 31 , 201 9 page 99 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 8.3 48 - pin lqfp (7x7x1. 4 mm footprint 2.0 mm) 1 12 48 h h ? controlling dimension : millimeters 0.10 0 7 0 0.004 1.00 0.75 0.60 0.45 0.039 0.030 0.024 0.018 9.10 9.00 8.90 0.358 0.354 0.350 0.50 0.20 0.25 1.45 1.40 0.10 0.15 1.35 0.008 0.010 0.057 0.055 0.026 7.10 7.00 6.90 0.280 0.276 0.272 0.004 0.006 0.053 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y 0 a a l 1 1 2 e 0.008 0.006 0.15 0.20 7 0.020 0.35 0.65 0.10 0.05 0.002 0.004 0.006 0.15 9.10 9.00 8.90 0.358 0.354 0.350 7.10 7.00 6.90 0.280 0.276 0.272 0.014 37 36 25 24 13
n u m icro ? j an 31 , 201 9 page 100 of 100 revision 1.01 nuc 2 00/ 2 2 0 datasheet 9 revision h istory r e vi sion d ate d escription v 1.00 june 07 , 2012 initial release v1 .01 j a n 31 , 201 9 updated typo error in description. important notice nuvoton products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. such applications are deemed , insecure usage. insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety sys tems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. all insecure usage shall be made at customers risk, and in the event that third parties lay claims to nuv oton as a result of customers insecure usage, customer shall indemnify the damages and liabilities thus incurred by nuvoton.

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